Computing in memory cell

1. A computing in memory cell, comprising:

a memory cell circuit;

a first semiconductor element having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first semiconductor element is adapted to receive a bias voltage corresponding to a first weight, and the control terminal of the first semiconductor element is adapted to be coupled to a computing word-line,

a second semiconductor element having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit, and the first terminal of the second semiconductor element is coupled to the second terminal of the first semiconductor element;

a third semiconductor element having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third semiconductor element is coupled to the second terminal of the second semiconductor element, the second terminal of the third semiconductor element is adapted to receive a reference voltage, and the control terminal of the third semiconductor element is adapted receive an inverted signal of the computing word-line; and

a fourth semiconductor element configured to selectively provide a weight resistance corresponding to a weight, wherein a first terminal of the fourth semiconductor element is adapted to be coupled to a first computing bit-line, a second terminal of the fourth semiconductor element is adapted to be coupled to a second computing bit-line, and a control terminal of the fourth semiconductor element is coupled to the second terminal of the second semiconductor element.

2. The computing in memory cell of claim 1 , wherein the memory cell circuit comprises:

a static random access memory cell having the first data node and a second data node;

a first switch having a first terminal coupled to the first data node, wherein a second terminal of the first switch is adapted to be coupled to a first data bit-line, and a control terminal of the first switch is adapted to be coupled to a data word-line; and

a second switch having a first terminal coupled to the second data node, wherein a second terminal of the second switch is adapted to be coupled to a second data bit-line, and a control terminal of the second switch is adapted to be coupled to the data word-line.

3. The computing in memory cell of claim 2 , wherein the static random access memory cell comprises:

a first transistor having a control terminal coupled to the first data node, wherein a first terminal of the first transistor is coupled to the second data node, and a second terminal of the first transistor is adapted to receive a reference voltage;

a second transistor having a control terminal coupled to the first data node, wherein a first terminal of the second transistor is coupled to the second data node, and a second terminal of the second transistor is adapted to receive a system voltage;

a third transistor having a control terminal coupled to the second data node, wherein a first terminal of the third transistor is coupled to the first data node, and a second terminal of the third transistor is adapted to receive the reference voltage; and

a fourth transistor having a control terminal coupled to the second data node, wherein a first terminal of the fourth transistor is coupled to the first data node, and a second terminal of the fourth transistor is adapted to receive the system voltage.

4. The computing in memory cell of claim 1 , wherein the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are all composed of N-channel metal oxide semiconductor transistors.

5. The computing in memory cell of claim 1 , wherein a voltage difference between the bias voltage and a voltage of the second computing bit-line is less than a threshold voltage of the fourth semiconductor element.