IP Library › Granted Patent US 11,742,261

Granted Patent B2

US 11,742,261 · App. 18/089,535 · Granted Aug 29, 2023

Nested architectures for enhanced heterogeneous integration

Inventors: Ravindranath Mahajan (Chandler, AZ); Debendra Mallik (Chandler, AZ); Sujit Sharan (Chandler, AZ); Digvijay Raorane (Chandler, AZ)

Assignee: Intel Corporation

H01L23/481 H01L21/565 H01L21/76898 H01L23/315 H01L23/3128 H01L23/34 H01L23/5383 H01L23/5386 H01L24/09 H01L24/17 H01L24/29 H01L24/73 H01L25/18 H01L2224/73253

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Quick Facts

Patent No.: US 11,742,261
App. No.: 18/089,535
Granted: Aug 29, 2023
Kind: B2

External Links

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Abstract

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

Claims (59)

1. An electronic package, comprising:

a base substrate having a first side and a second side, the second side opposite the first side;

a component in a cavity of the base substrate, the component having a first side and a second side, the second side opposite the first side, and the component having a first sidewall and a second sidewall between the first side and the second side, the first sidewall laterally opposite the second sidewall;

a first plurality of through substrate vias in the base substrate, the first plurality of through substrate vias laterally spaced apart from the first sidewall of the component;

a second plurality of through substrate vias in the base substrate, the second plurality of through substrate vias laterally spaced apart from the second sidewall of the component;

a mold layer having a first portion laterally between the first plurality of through substrate vias and the first sidewall of the component, the first portion of the mold layer in contact with the first sidewall of the component, and the mold layer having a second portion laterally between the second plurality of through substrate vias and the second sidewall of the component, the second portion of the mold layer in contact with the second sidewall of the component;

a redistribution layer on the first side of the base substrate, the redistribution layer vertically over the component, vertically over the first plurality of through substrate vias, and vertically over the second plurality of through substrate vias;

a first plurality of interconnects coupling the first side of the component to the redistribution layer;

a first die over a first portion of the redistribution layer, the first die over the first plurality of through substrate vias and over a first portion of the component;

a second plurality of interconnects coupling the first die to the first portion of the redistribution layer;

a second die over a second portion of the redistribution layer, the second die over the second plurality of through substrate vias and over a second portion of the component;

a third plurality of interconnects coupling the second die to the second portion of the redistribution layer; and

a plurality of bumps beneath the second side of the base substrate, the plurality of bumps vertically beneath the second side of the component, vertically beneath the first plurality of through substrate vias, and vertically beneath the second plurality of through substrate vias.

2. The electronic package of claim 1 , wherein the redistribution layer is electrically coupled to the first plurality of through substrate vias and to the second plurality of through substrate vias.

3. The electronic package of claim 1 , wherein the redistribution layer is electrically coupled to the component by first level interconnects.

4. The electronic package of claim 1 , further comprising:

a second mold layer laterally between the first die and the second die, the second mold layer beneath the first die and beneath the second die.

5. The electronic package of claim 4 , wherein the second mold layer has an uppermost surface at a same level as an uppermost surface of the first die and at a same level as an uppermost surface of the second die.

6. The electronic package of claim 1 , wherein the base substrate is a silicon substrate.

7. The electronic package of claim 1 , wherein the mold layer is not in contact with the first plurality of through substrate vias and is not in contact with the second plurality of through substrate vias.

8. The electronic package of claim 1 , wherein the mold layer has a bottommost surface at a same level as a bottommost surface of the component.

9. An electronic package, comprising:

a base substrate having a first side and a second side, the second side opposite the first side;

an embedded multi-die interconnect bridge in a cavity of the base substrate, the embedded multi-die interconnect bridge having a first side and a second side, the second side opposite the first side, and the embedded multi-die interconnect bridge having a first sidewall and a second sidewall between the first side and the second side, the first sidewall laterally opposite the second sidewall;

first vias in the base substrate, the first vias laterally spaced apart from the first sidewall of the embedded multi-die interconnect bridge;

second vias in the base substrate, the second vias laterally spaced apart from the second sidewall of the embedded multi-die interconnect bridge;

a first mold layer having a first portion laterally between the first vias and the first sidewall of the embedded multi-die interconnect bridge, the first portion of the first mold layer in contact with the first sidewall of the embedded multi-die interconnect bridge, and the first mold layer having a second portion laterally between the second vias and the second sidewall of the embedded multi-die interconnect bridge, the second portion of the first mold layer in contact with the second sidewall of the embedded multi-die interconnect bridge;

a redistribution layer on the first side of the base substrate, the redistribution layer electrically coupled to the embedded multi-die interconnect bridge, the redistribution layer on and electrically coupled to the first vias, and the redistribution layer on and electrically coupled to the second vias;

a first plurality of interconnects coupling the first side of the embedded multi-die interconnect bridge to the redistribution layer;

a first die over a first portion of the redistribution layer, the first die over the first vias and over a first portion of the embedded multi-die interconnect bridge;

a second plurality of interconnects coupling the first die to the first portion of the redistribution layer;

a second die over a second portion of the redistribution layer, the second die over the second vias and over a second portion of the embedded multi-die interconnect bridge;

a third plurality of interconnects coupling the second die to the second portion of the redistribution layer;

a second mold layer laterally between the first die and the second die, the second mold layer beneath the first die and beneath the second die; and

a plurality of bumps beneath the second side of the base substrate, the plurality of bumps vertically beneath the second side of the embedded multi-die interconnect bridge, vertically beneath the first vias, and vertically beneath the second vias.

10. The electronic package of claim 9 , wherein the second mold layer has an uppermost surface at a same level as an uppermost surface of the first die and at a same level as an uppermost surface of the second die.

11. The electronic package of claim 9 , wherein the base substrate is a silicon substrate.

12. The electronic package of claim 9 , wherein the first mold layer is not in contact with the first vias and is not in contact with the second vias.

13. A method of fabricating an electronic package, the method comprising:

forming a base substrate having a first side and a second side, the second side opposite the first side;

providing a component in a cavity of the base substrate, the component having a first side and a second side, the second side opposite the first side, and the component having a first sidewall and a second sidewall between the first side and the second side, the first sidewall laterally opposite the second sidewall;

forming a first plurality of through substrate vias in the base substrate, the first plurality of through substrate vias laterally spaced apart from the first sidewall of the component;

forming a second plurality of through substrate vias in the base substrate, the second plurality of through substrate vias laterally spaced apart from the second sidewall of the component;

forming a mold layer having a first portion laterally between the first plurality of through substrate vias and the first sidewall of the component, the first portion of the mold layer in contact with the first sidewall of the component, and the mold layer having a second portion laterally between the second plurality of through substrate vias and the second sidewall of the component, the second portion of the mold layer in contact with the second sidewall of the component;

forming a redistribution layer on the first side of the base substrate, the redistribution layer vertically over the component, vertically over the first plurality of through substrate vias, and vertically over the second plurality of through substrate vias;

forming a first plurality of interconnects coupling the first side of the component to the redistribution layer;

providing a first die over a first portion of the redistribution layer, the first die over the first plurality of through substrate vias and over a first portion of the component;

forming a second plurality of interconnects coupling the first die to the first portion of the redistribution layer;

providing a second die over a second portion of the redistribution layer, the second die over the second plurality of through substrate vias and over a second portion of the component;

forming a third plurality of interconnects coupling the second die to the second portion of the redistribution layer; and

forming a plurality of bumps beneath the second side of the base substrate, the plurality of bumps vertically beneath the second side of the component, vertically beneath the first plurality of through substrate vias, and vertically beneath the second plurality of through substrate vias.

14. The method of claim 13 , wherein the redistribution layer is electrically coupled to the first plurality of through substrate vias and to the second plurality of through substrate vias.

15. The method of claim 13 , wherein the redistribution layer is electrically coupled to the component by first level interconnects.

16. The method of claim 13 , further comprising:

forming a second mold layer laterally between the first die and the second die, the second mold layer beneath the first die and beneath the second die.

17. The method of claim 16 , wherein the second mold layer has an uppermost surface at a same level as an uppermost surface of the first die and at a same level as an uppermost surface of the second die.

18. The method of claim 13 , wherein the base substrate is a silicon substrate.

19. The method of claim 13 , wherein the mold layer is not in contact with the first plurality of through substrate vias and is not in contact with the second plurality of through substrate vias.

20. The method of claim 13 , wherein the mold layer has a bottommost surface at a same level as a bottommost surface of the component.

Continuity (2)

Continuation 16291314 · Mar 4, 2019

Related Publication 20230133429A1 · May 4, 2023

Cited By (1)

US 12,243,806