Alignment mark design for packages

1. A method comprising:

forming a first dielectric layer;

performing a plating process to form an alignment mark over the first dielectric layer;

placing a device die over the first dielectric layer, wherein the placing is performed using the alignment mark for aligning a position of the device die;

encapsulating the alignment mark in an encapsulant;

forming a second dielectric layer over and contacting the alignment mark and the encapsulant; and

forming a plurality of redistribution lines extend into the second dielectric layer and electrically connecting to the device die, wherein the plurality of redistribution lines are formed using the alignment mark for aligning positions, and wherein at a time after the plurality of redistribution lines are formed, the alignment mark is covered by the second dielectric layer, and wherein at a time after the plurality of redistribution lines are formed, a conductive feature is formed to comprise the alignment mark and an additional redistribution line electrically connected to the alignment mark, and wherein the conductive feature is fully insulated in dielectric features.

2. The method of claim 1 , wherein the forming the plurality of redistribution lines comprises:

forming a seed layer; and

plating a metallic material on the seed layer.

3. The method of claim 2 , wherein the seed layer is in physical contact with a metal pillar of the device die, and the seed layer is insulated from the alignment mark by the second dielectric layer.

4. The method of claim 1 , wherein an entire top surface of the alignment mark is in physical contact with the second dielectric layer.

5. The method of claim 1 further comprising, in a common process for forming the alignment mark, forming a plurality of metal posts, wherein the plurality of redistribution lines are electrically connected to the plurality of metal posts.

6. The method of claim 1 , wherein at a time after the plurality of redistribution lines are formed, the alignment mark is electrically floating.

7. The method of claim 1 further comprising:

before the forming the plurality of redistribution lines,

forming an opening exposing the device die, wherein one of the plurality of redistribution lines extends into the opening to connect to the device die, and wherein the forming the opening is performed using the alignment mark for alignment.

8. The method of claim 7 , wherein at a time after the plurality of redistribution lines is formed, the alignment mark in the encapsulant is overlapped by the second dielectric layer, and a top surface of the alignment mark is in contact with the second dielectric layer.

9. The method of claim 1 further comprising forming a plurality of dielectric layers covering the alignment mark and the device die, wherein the plurality of redistribution lines further extend into the plurality of dielectric layers.

10. The method of claim 1 further comprising performing a die-saw process to separate the encapsulant into a plurality of packages, wherein the alignment mark is in one of the plurality of packages.

11. The method of claim 1 , wherein the encapsulating the alignment mark in the encapsulant comprises molding the alignment mark in a molding compound.

12. A method comprising:

forming a first redistribution line;

forming an alignment mark over and electrically connecting to the first redistribution line, wherein the forming the alignment mark comprises plating;

depositing a dielectric layer over the alignment mark; and

forming a plurality of redistribution lines comprising first portions over the dielectric layer, and second portions extending into the dielectric layer, wherein the plurality of redistribution lines are formed using the alignment mark for aligning, and wherein at a time after the plurality of redistribution lines are formed, a conductive feature comprising the alignment mark and the first redistribution line is fully insulated in dielectric features.

13. The method of claim 12 further comprising:

forming a plurality of openings in the dielectric layer, with the second portions of the plurality of redistribution lines being in the plurality of openings, wherein the forming the plurality of openings is performed using the alignment mark for aligning positions.

14. The method of claim 12 , wherein the first redistribution line is electrically coupled to the alignment mark, and wherein both of the alignment mark and the first redistribution line are electrically floating.

15. The method of claim 12 further comprising a die-saw process to form a package, wherein in the package, the alignment mark is electrically floating.

16. The method of claim 12 further comprising forming a plurality of metal posts, wherein each of the plurality of metal posts electrically interconnects features on opposite sides of the encapsulant, and wherein the plurality of metal posts define a rectangular design area in a top view of the plurality of metal posts and the alignment mark, and the alignment mark is outside of the rectangular design area.

17. A method comprising:

forming a first redistribution line;

forming a first dielectric layer covering the first redistribution line;

forming an electrically conductive via in the first dielectric layer;

forming an alignment mark over and joined to the electrically conductive via;

encapsulating a device die and the alignment mark in an encapsulant;

forming a second dielectric layer over and contacting the device die and the alignment mark; and

forming a plurality of redistribution lines over the encapsulant, with the alignment mark used for aligning positions of the plurality of redistribution lines, wherein the plurality of redistribution lines comprise a portion extending into the second dielectric layer to contact a top surface of a metal pillar in the device die, and wherein after the plurality of redistribution lines are formed, a combined conductive region comprising the alignment mark and the first redistribution line is fully insulated in dielectric features.

18. The method of claim 17 , wherein the electrically conductive via and the alignment mark are formed in a single plating process.

19. The method of claim 17 , wherein after the plurality of redistribution lines are formed, an entire top surface of the alignment mark is in contact with the first dielectric layer.

20. The method of claim 17 , wherein at a time after the plurality of redistribution lines are formed, the alignment mark is electrically floating.