Gate-all-around integrated circuit structures having oxide sub-fins
Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.
1. An integrated circuit structure, comprising:
an oxide sub-fin structure having a top and sidewalls;
an oxidation catalyst layer on the top and sidewalls of the oxide sub-fin structure;
a vertical arrangement of nanowires vertically overlapping with the oxide sub-fin structure;
a gate stack surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.
2. The integrated circuit structure of claim 1 , wherein the oxidation catalyst layer comprises aluminum oxide.
3. The integrated circuit structure of claim 1 , wherein the oxidation catalyst layer comprises lanthanum oxide.
4. The integrated circuit structure of claim 1 , further comprising:
epitaxial source or drain structures at ends of the vertical arrangement of nanowires.
5. The integrated circuit structure of claim 4 , wherein the epitaxial source or drain structures are discrete epitaxial source or drain structures.
6. The integrated circuit structure of claim 4 , wherein the epitaxial source or drain structures are non-discrete epitaxial source or drain structures.
7. The integrated circuit structure of claim 4 , wherein the gate stack has dielectric sidewall spacers, and the epitaxial source or drain structures are embedded epitaxial source or drain structures extending beneath the dielectric sidewall spacers of the gate stack.
8. The integrated circuit structure of claim 4 , further comprising:
a pair of conductive contact structures coupled to the epitaxial source or drain structures.
9. The integrated circuit structure of claim 8 , wherein the pair of conductive contact structures is an asymmetric pair of conductive contact structures.
10. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.