Method and apparatus for optimizing memory power

1. A method for optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method, comprising:

setting a ratio and sizes of a pull-up NMOS transistor and a pull-down NMOS transistor included in an N-over-N driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and

setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern,

wherein the N-over-N driver includes a plurality of pull-up NMOS transistors and a plurality of pull-down NMOS transistors, each of the pull-up transistors and the pull-down transistors having a binary size, and

wherein the ratio and sizes of the pull-up NMOS transistor and the pull-down NMOS transistor is determined by selecting one or more pull-up transistors or one or more pull-down transistors from among the plurality of pull-up transistors and the plurality of pull-down transistors.

2. The method of claim 1 , wherein the setting of the ratio and the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor comprises:

sequentially transmitting DC voltages corresponding to data of 00, 01, 10, and 11 from the N-over-N driver to the sampler;

increasing the reference voltage of the sampler and measuring a first output voltage of the sampler corresponding to each of the DC voltages;

setting a voltage difference value having a smallest voltage difference of the first output voltage as a first voltage difference value;

repeating the measurement of the first voltage difference value by changing the size of the pull-down NMOS transistor; and

setting the size of the pull-down NMOS transistor having a greatest value among the measured first voltage difference values as a size of a final pull-down NMOS transistor.

3. The method of claim 2 , wherein the setting of the ratio and the size of the pull-up NMOS transistor and the pull-down NMOS transistor further comprises:

repeatedly measuring a second output voltage of the sampler by changing the size of the pull-up NMOS transistor and the reference voltage of the sampler; and

setting the size of the pull-up NMOS transistor at a point in time when a sign of the second output voltage is inverted to a size of the final pull-up NMOS transistor.

4. The method of claim 3 , wherein the setting of the reference voltage of the sampler and the phase interpolator (PI) digital code value further comprises:

setting an arithmetic mean value of DC voltage values having a smallest voltage difference of the first output voltage as a first reference voltage; and

setting the first reference voltage as a final reference voltage of the sampler.

5. The method of claim 4 , wherein the setting of the reference voltage of the sampler and the phase interpolator (PI) digital code value further comprises:

increasing the first reference voltage and measuring a third output voltage value of the sampler according to the SBR pattern;

changing the PI digital code value and repeatedly measuring the third output voltage value of the sampler according to the SBR pattern; and

setting the PI digital code value having a greatest value among the measured third output voltage values as a final PI digital code value.

6. The method of claim 5 , wherein the setting of the reference voltage of the sampler and the phase interpolator (PI) digital code value further comprises:

increasing the first reference voltage value and measuring a fourth output voltage value of the sampler according to the SBR pattern;

changing a delay line (DCDL) digital code value and repeatedly measuring the fourth output voltage value of the sampler according to the SBR pattern; and

setting the DCDL digital code value having a greatest value among the measured fourth output voltage values as a final DCDL digital code value.

7. The method of claim 6 ,

wherein the setting of the ratio and the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor further comprises setting a ratio and sizes of a pull-up NMOS transistor and a pull-down NMOS transistor of the feed forward equalizer (FFE), and

wherein the setting of the ratio and the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the FFE comprises:

changing the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the FFE while maintaining a difference value between the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the N-over-N driver;

changing the PI digital code value by 64 from the final PI digital code value;

repeatedly measuring a fifth output voltage value of the sampler according to the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the FFE and the change of the final PI digital code value;

measuring a sum of remaining voltage values excluding a greatest voltage value among the measured fifth output voltage values; and

setting the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the FFE corresponding to a case in which the sum of the remaining voltage values is the smallest as a size of the final NMOS transistor of the FFE.

8. An apparatus for optimizing memory power which uses pulse-amplitude modulation-4 (PAM-4) method, the apparatus comprising:

a memory controller configured to set a ratio and sizes of a pull-up NMOS transistor and a pull-down NMOS transistor included in an N-over-N driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and

a memory digital block configured to set a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern,

wherein the N-over-N driver includes a plurality of pull-up NMOS transistors and a plurality of pull-down NMOS transistors, each of the pull-up transistors and the pull-down transistors having a binary size, and

wherein the ratio and sizes of the pull-up NMOS transistor and the pull-down NMOS transistor is determined by selecting one or more pull-up transistors or one or more pull-down transistors from among the plurality of pull-up transistors and the plurality of pull-down transistors.

9. The apparatus of claim 8 ,

wherein the memory controller sets the ratio and the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor, sequentially transmits DC voltages corresponding to data of 00, 01, 10, and 11 from the N-over-N driver to the sampler, increases the reference voltage of the sampler and measuring a first output voltage of the sampler corresponding to each of the DC voltages, sets a voltage difference value having a smallest voltage difference of the first output voltage as a first voltage difference value, repeats the measurement of the first voltage difference value by changing the size of the pull-down NMOS transistor, and sets the size of the pull-down NMOS transistor having a greatest value among the measured first voltage difference values as a size of a final pull-down NMOS transistor.

10. The apparatus of claim 9 ,

wherein the memory controller sets the ratio and the size of the pull-up NMOS transistor and the pull-down NMOS transistor, repeatedly measures a second output voltage of the sampler by changing the size of the pull-up NMOS transistor and the reference voltage of the sampler, and sets the size of the pull-up NMOS transistor at a point in time when a sign of the second output voltage is inverted to a size of the final pull-up NMOS transistor.

11. The apparatus of claim 10 ,

wherein the memory digital block sets an arithmetic mean value of DC voltage values having a smallest voltage difference of the first output voltage as a first reference voltage, and sets the first reference voltage as a final reference voltage of the sampler.

12. The apparatus of claim 11 ,

wherein the memory digital block increases the first reference voltage and measuring a third output voltage value of the sampler according to the SBR pattern, changes the PI digital code value and repeatedly measuring the third output voltage value of the sampler according to the SBR pattern, and sets the PI digital code value having a greatest value among the measured third output voltage values as a final PI digital code value.

13. The apparatus of claim 12 ,

wherein the memory digital block increases the first reference voltage value and measuring a fourth output voltage value of the sampler according to the SBR pattern, changes a delay line (DCDL) digital code value and repeatedly measuring the fourth output voltage value of the sampler according to the SBR pattern, and sets the DCDL digital code value having a greatest value among the measured fourth output voltage values as a final DCDL digital code value.

14. The apparatus of claim 13 ,

wherein the memory controller changes the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the FFE while maintaining a difference value between the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the N-over-N driver, changing the PI digital code value by 64 from the final PI digital code value, repeatedly measures a fifth output voltage value of the sampler according to the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the FFE and the change of the final PI digital code value, measures a sum of remaining voltage values excluding a greatest voltage value among the measured fifth output voltage values, and sets the sizes of the pull-up NMOS transistor and the pull-down NMOS transistor of the FFE corresponding to a case in which the sum of the remaining voltage values is the smallest as a size of the final NMOS transistor of the FFE.