Differential-signal-detection circuit
One example discloses a differential-signal-detection circuit, comprising: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive the first differential output signal and generate a first comparator output signal; a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal.
1. A differential-signal-detection circuit, comprising:
an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal;
a first comparator coupled to receive the first differential output signal and generate a first comparator output signal;
a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and
an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal;
wherein the input stage includes a first path having a first node and a second node, and a second path having a third node and a fourth node;
wherein a first resistance is between the first node and the second node;
wherein a second resistance is between the third node and the fourth node;
wherein a first current source is coupled to the second node;
wherein a second current source is coupled to the fourth node;
wherein the first resistance and the first current source are configured to set a first threshold voltage; and
wherein if the differential input signal is greater than the first threshold voltage, then the differential-signal-detection signal is generated by the output stage.
2. The circuit of claim 1 :
wherein the second differential output signal is generated from the second node and the third node; and
wherein the first differential output signal is generated from the first node and the fourth node.
3. The circuit of claim 1 :
wherein the first and second resistances are equal.
4. The circuit of claim 1 :
wherein the first and second resistances are variable in response to a controller signal.
5. The circuit of claim 1 :
wherein the first and second current source currents are equal.
6. The circuit of claim 1 :
wherein the first and second current source currents are variable in response to a controller signal.
7. The circuit of claim 1 :
wherein the first resistance and the first current source are configured to set the first threshold voltage;
wherein the second resistance and the second current source are configured to set a second threshold voltage; and
wherein if the differential input signal is greater than either the first or second threshold voltages, then the differential-signal-detection signal is generated by the output stage.
8. The circuit of claim 1 :
wherein the first threshold voltage=(n*Vbg/R)*R1;
wherein (n*Vbg/R)=the first current source current and R1=the first resistance; and
wherein “n” is a variable integer, Vbg is an bandgap reference voltage, R is an internal equivalent resistance of the first current source.
9. The circuit of claim 7 :
wherein the first threshold voltage and the second threshold voltage are equal.
10. The circuit of claim 7 :
wherein the first threshold voltage and the second threshold voltage are different.
11. The circuit of claim 1 :
wherein the circuit is embedded in a squelch-detector; and
wherein the differential-signal-detection signal logic-high corresponds to an un-squelched state, and the differential-signal-detection signal logic-low corresponds to an squelched state.
12. The circuit of claim 1 :
wherein the circuit is embedded in a disconnect-detector; and
wherein the differential-signal-detection signal logic-high corresponds to a connected state, and the differential-signal-detection signal logic-low corresponds to a disconnected state.
13. The circuit of claim 1 :
wherein a third current source is coupled to the first node; and
wherein a fourth current source is coupled to the third node.
14. The circuit of claim 1 :
wherein a first transistor is coupled to the first node and a first end of the differential input signal; and
wherein a second transistor is coupled to the third node and a second end of the differential input signal.
15. The circuit of claim 1 :
wherein the circuit is embedded in a repeater-circuit; and
wherein the differential input signal is either an eUSB or USB signal.
16. A differential-signal-detection circuit, comprising:
an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal;
a first comparator coupled to receive the first differential output signal and generate a first comparator output signal;
a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and
an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal;
wherein the input stage includes a first path having a first node and a second node, and a second path having a third node and a fourth node;
wherein a first resistance is between the first node and the second node;
wherein a second resistance is between the third node and the fourth node;
wherein a first current source is coupled to the second node;
wherein a second current source is coupled to the fourth node;
wherein a third current source is coupled to the first node; and
wherein a fourth current source is coupled to the third node.
17. An eUSB to USB repeater-circuit, comprising:
a differential-signal-detection circuit;
wherein the differential-signal-detection circuit includes,
an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal;
a first comparator coupled to receive the first differential output signal and generate a first comparator output signal;
a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and
an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal;
wherein the input stage includes a first path having a first node and a second node, and a second path having a third node and a fourth node;
wherein a first resistance is between the first node and the second node;
wherein a second resistance is between the third node and the fourth node;
wherein a first current source is coupled to the second node;
wherein a second current source is coupled to the fourth node;
wherein the first resistance and the first current source are configured to set a first threshold voltage;
wherein if the differential input signal is greater than the first threshold voltage, then the differential-signal-detection signal is generated by the output stage; and
wherein the differential input signal is either an eUSB or USB signal.