Microprocessor that fuses load and compare instructions
Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.
1. A computer-implemented method (CIM) comprising:
receiving, by an instruction fetch unit of a load-store architecture style processor, a load instruction including an RT field value;
receiving, by the instruction fetch unit, a compare-immediate instruction including an RA field value;
determining, by the instruction fetch unit, that the RT field value is the same as the RA field value; and
responsive to the determination that the RA field value is the same as the RT field value, fusing, by the instruction fetch unit, the load instruction and the compare-immediate instruction to form a single fused instruction determining, by the instruction fetch unit, that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1;
wherein the fusion is further responsive to the determination that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1.
2. The CIM of claim 1 wherein the load instruction and the compare-immediate instruction are consecutive instructions.
3. A non-transitory computer program product (CPP) comprising:
a set of storage device(s); and
computer code stored collectively in the set of storage device(s), with the computer code including data and instructions to cause a processor(s) set to perform at least the following operations:
receiving, by an instruction fetch unit of a load-store architecture style processor, a load instruction including an RT field value,
receiving, by the instruction fetch unit, a compare-immediate instruction including an RA field value,
determining, by the instruction fetch unit, that the RT field value is the same as the RA field value, and
responsive to the determination that the RA field value is the same as the RT field value, fusing, by the instruction fetch unit, the load instruction and the compare-immediate instruction to form a single fused instruction determining, by the instruction fetch unit, that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1,
wherein the fusion is further responsive to the determination that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1.
4. The CPP of claim 3 wherein the load instruction and the compare-immediate instruction are consecutive instructions.
5. A computer system (CS) comprising:
a processor(s) set;
a set of storage device(s); and
computer code stored collectively in the set of storage device(s), with the computer code including data and instructions to cause the processor(s) set to perform at least the following operations:
receiving, by an instruction fetch unit of a load-store architecture style processor, a load instruction including an RT field value,
receiving, by the instruction fetch unit, a compare-immediate instruction including an RA field value,
determining, by the instruction fetch unit, that the RT field value is the same as the RA field value, and
responsive to the determination that the RA field value is the same as the RT field value, fusing, by the instruction fetch unit, the load instruction and the compare-immediate instruction to form a single fused instruction determining, by the instruction fetch unit, that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1,
wherein the fusion is further responsive to the determination that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1.
6. The CS of claim 5 wherein the load instruction and the compare-immediate instruction are consecutive instructions.