IP Library › Granted Patent US 11,748,536
Granted Patent B2
US 11,748,536 · App. 17/297,745 · Granted Sep 5, 2023

Automated microprocessor design

Inventors: Yunsup Lee (Redwood City, CA); Michael Cave (San Mateo, CA)
Assignee: SiFive, Inc.
G06F30/327G06F30/33G06F2115/02G06F2115/12
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Quick Facts
Patent No.
US 11,748,536
App. No.
17/297,745
Granted
Sep 5, 2023
Kind
B2
Abstract

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

Claims (10)

1. A system comprising:

a web application server configured to generate a design parameters data structure based on input received, wherein the design parameters data structure includes values of design parameters of an integrated circuit design, configured to display an auto-updating block diagram of a template design reflecting changes to values of the design parameters of the integrated circuit design, and configured to issue a command to build the integrated circuit design; and

a controller configured to, responsive to the command to build the integrated circuit design, access the design parameters data structure, invoke a register-transfer level service module with the design parameters data structure to obtain a register-transfer level data structure, invoke a software development kit service module with the register-transfer level data structure to obtain a software development kit, invoke a physical design service module with the register-transfer level data structure to obtain a physical design data structure, invoke a verification service module to obtain a test plan, and invoke tests for the integrated circuit design based on the test plan, the register-transfer level data structure, the software development kit, and the physical design data structure to obtain a set of test results; and

a machine learning based design iterator configured to take as input both, values of design parameters of the design parameters data structure, and a feedback signal based on a design criterion of the design parameters data structure and the set of test results, to obtain a modified design parameters data structure, and configured to issue a command to the controller to cause the controller to build a second integrated circuit design based on the modified design parameters data structure.

2. The system of claim 1 , wherein the machine learning based design iterator has been trained using training data that includes prior inputs to the machine learning based design iterator that included a respective feedback signal based on test results obtained by the controller.

3. The system of claim 1 , wherein the feedback signal includes a difference between a test result from the set of test results and a threshold of the design criterion.

4. The system of claim 1 , wherein the feedback signal includes a ratio between a test result from the set of test results and a threshold of the design criterion.

5. The system of claim 1 , wherein a provenance stamp is embedded within the register-transfer level data structure, wherein the provenance stamp includes metadata indicating circumstances of reception of a design data structure used to generate the register-transfer level data structure.

6. The system of claim 5 , wherein the provenance stamp includes at least one of a cryptographic signature, a hash, and a notarization.

7. The system of claim 1 , wherein a provenance stamp is embedded within the physical design data structure, wherein the provenance stamp includes metadata indicating circumstances of reception of a design data structure used to generate the physical design data structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2021
From: LEE, YUNSUP; CAVE, MICHAEL
To: SIFIVE, INC.
Reel/Frame 056373/0337 →
Continuity (2)
Provisional Application 62772626 · Nov 28, 2018
Related Publication 20220050946A1 · Feb 17, 2022