Display panel, driving method for same, and display apparatus

1. A display panel, comprising a plurality of pixel circuits, wherein each of the plurality of pixel circuits comprises:

a drive transistor, comprising a gate electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node;

a voltage writing circuit, electrically connected to a first scanning signal line, a data line, and the second node, respectively; and

a threshold compensation circuit, electrically connected to a second scanning signal line, the third node, and the first node, respectively;

wherein a driving cycle of each of the plurality of the pixel circuits comprises a writing phase and at least one holding phase, the writing phase comprises a first non-light-emission period, and the at least one holding phase comprises a second non-light-emission period;

wherein the voltage writing circuit is configured to write a display voltage into the second node in the first non-light-emission period in response to an enable level of a first scanning signal, and write a node reset voltage into the second node in at least part of the second non-light-emission period in response to the enable level of the first scanning signal; and

wherein the threshold compensation circuit is configured to compensate for a threshold voltage of the drive transistor in the first non-light-emission period in response to an enable level of a second scanning signal, and

the display panel further comprising a plurality of circuit rows arranged along a first direction,

wherein each circuit row of the plurality of circuit rows comprises pixel circuits arranged along a second direction, and the first direction intersects the second direction; and

wherein one first scanning signal line is electrically connected to voltage writing circuits of the pixel circuits in x circuit rows of the plurality of circuit rows, x being a positive integer greater than or equal to 1.

2. The display panel according to claim 1 ,

wherein each of the plurality of pixel circuits further comprises a light-emission control circuit, which is electrically connected to a light-emission control signal line, a power signal line, the second node, the third node, and an anode of a light-emission element;

wherein the writing phase further comprises a first light-emission period; the at least one holding phase further comprises a second light-emission period; the light-emission control circuit is configured to transmit a driving current to the anode of the light-emission element in the first light-emission period and in the second light-emission period in response to an enable level of a light-emission control signal; and

wherein one light-emission control signal line is electrically connected to light-emission control circuits of the pixel circuits in y circuit rows of the plurality of circuit rows, y being a positive integer greater than or equal to 1.

3. The display panel according to claim 2 , wherein x=y, and x>2.

4. The display panel according to claim 2 , wherein x=y;

the display panel further comprises a control circuit; a control terminal of the control circuit is electrically connected to the light-emission control signal line; an input terminal of the control circuit is electrically connected to a first fixed potential signal line, and the first fixed potential signal line is used for providing the enable level of the first scanning signal; and an output terminal of the control circuit is electrically connected to the first scanning signal line; and

the first scanning signal line and the light-emission control signal line electrically connected to a same control circuit are electrically connected to a same x circuit rows of the plurality of circuit rows.

5. The display panel according to claim 4 , wherein

the control circuit comprises a control transistor, a gate of the control transistor is electrically connected to the light-emission control signal line, a first electrode of the control transistor is electrically connected to the first fixed potential signal line, and a second electrode of the control transistor is electrically connected to the first scanning signal line.

6. The display panel according to claim 2 , wherein

x>y; and

for the x circuit rows of the plurality of circuit rows electrically connected to a same first scanning signal line, an overlapping range exists between non-enable levels of at least two light-emission control signals corresponding to the x circuit rows of the plurality of circuit rows, and the enable level of the first scanning signal is within the overlapping range.

7. The display panel according to claim 1 , wherein

each of the plurality of pixel circuits further comprises a first reset circuit, and the first reset circuit is electrically connected between the first reset signal line and an anode of a light-emission element; and the first reset circuit is configured to write a first reset voltage into the anode of the light-emission element in the first non-light-emission period and in at least a part of the second non-light-emission period in response to an enable level of a third scanning signal.

8. The display panel according to claim 7 , wherein

the first scanning signal line is further used for providing the third scanning signal, and the first reset circuit is electrically connected to the first scanning signal line.

9. The display panel according to claim 7 , wherein

the first reset circuit is electrically connected to a third scanning signal line for providing the third scanning signal.

10. The display panel according to claim 9 , wherein

the display panel comprises the plurality of circuit rows arranged along the first direction, each circuit row of the plurality of circuit rows comprises pixel circuits arranged along the second direction, and the first direction intersects the second direction; and

the third scanning signal line is electrically connected to the first reset circuit of the pixel circuit in k of the plurality of circuit rows respectively, k is a positive integer greater than or equal to 1.

11. The display panel according to claim 10 , wherein

each of the plurality of pixel circuits further comprises a light-emission control circuit; the light-emission control circuit is electrically connected to a light-emission control signal line, a power signal line, the second node, the third node, and the anode of the light-emission element; the writing phase further comprises a first light-emission period; the at least one holding phase further comprises a second light-emission period; and the light-emission control circuit is configured to transmit a driving current to the anode of the light-emission element in the first light-emission period and in the second light-emission period in response to an enable level of a light-emission control signal;

one light-emission control signal line is electrically connected to the light-emission control circuits of the pixel circuits in y circuit rows of the plurality of circuit rows, y being a positive integer greater than or equal to 1; and

k>y, and for k circuit rows of the plurality of circuit rows electrically connected to a same third scanning signal line, an overlapping range exists between non-enable levels of at least two light-emission control signals corresponding to the k circuit rows of the plurality circuit rows, and the enable level of the third scanning signal is within the overlapping range.

12. The display panel according to claim 1 , wherein

each of the plurality of pixel circuits further comprises a second reset circuit; the second reset circuit is electrically connected to a fourth scanning signal line, a second reset signal line, and the first node; and the second reset circuit is configured to write a second reset voltage into the first node in the first non-light-emission period in response to an enable level of a fourth scanning signal.

13. A method for driving a display panel comprises a plurality of pixel circuits, wherein each of the plurality of pixel circuits comprises:

a drive transistor, comprising a gate electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node;

a voltage writing circuit, electrically connected to a first scanning signal line, a data line, and the second node, respectively; and

a threshold compensation circuit, electrically connected to a second scanning signal line, the third node, and the first node, respectively;

wherein a driving cycle of each of the plurality of the pixel circuits comprises a writing phase and at least one holding phase, the writing phase comprises a first non-light-emission period, and the at least one holding phase comprises a second non-light-emission period;

wherein the voltage writing circuit is configured to write a display voltage into the second node in the first non-light-emission period in response to an enable level of a first scanning signal, and write a node reset voltage into the second node in at least part of the second non-light-emission period in response to the enable level of the first scanning signal; and

wherein the threshold compensation circuit is configured to compensate for a threshold voltage of the drive transistor in the first non-light-emission period in response to an enable level of a second scanning signal;

the display panel further comprising a plurality of circuit rows arranged along a first direction,

wherein each circuit row of the plurality of circuit rows comprises pixel circuits arranged along a second direction, and the first direction intersects the second direction; and

wherein one first scanning signal line is electrically connected to voltage writing circuits of the pixel circuits in x circuit rows of the plurality of circuit rows, x being a positive integer greater than or equal to 1; and

wherein the method comprises

driving each of the plurality of pixel circuits to control a light-emission element to emit light, wherein a driving cycle of each of the plurality of pixel circuits comprises the writing phase and the at least one holding phase, the writing phase comprises the first non-light-emission period, and the at least one holding phase comprises the second non-light-emission period;

in the first non-light-emission period, writing, by the voltage writing circuit, the display voltage into the second node in response to the enable level of the first scanning signal; and compensating, by the threshold compensation circuit, for the threshold voltage of the drive transistor in response to the enable level of the second scanning signal; and

in at least part of the second non-light-emission period, writing, by the voltage writing circuit, the node reset voltage into the second node in response to the enable level of the first scanning signal.

14. The method according to claim 13 , wherein

an enable frequency f1 of the first scanning signal satisfies f1>30 Hz.

15. The method according to claim 13 , wherein

each of the plurality of pixel circuits further comprises a light-emission control circuit; and the light-emission control circuit is electrically connected to a light-emission control signal line, a power signal line, the second node, a third node, and an anode of a light-emission element, respectively; and

the writing phase further comprises a first light-emission period, the at least one holding phase further comprises a second light-emission period, and the driving method further comprises: transmitting, by the light-emission control circuit, a driving current to the anode of the light-emission element in the first light-emission period and in the second light-emission period in response to an enable level of the light-emission control signal;

wherein an enable frequency of the first scanning signal is equal to an enable frequency of the light-emission control signal.

16. The method according to claim 13 , wherein

the node reset voltage is a fixed voltage.

17. The method according to claim 16 , wherein

the fixed voltage is V1, and 3V<V1<5V.

18. The method according to claim 13 , wherein

the display panel comprises the plurality of circuit rows arranged along the first direction, each circuit row of the plurality of circuit rows comprises pixel circuits arranged along a second direction, and the first direction intersects the second direction; and

the first scanning signal line is electrically connected to the voltage writing circuits of the pixel circuits in x circuit rows of the plurality of circuit rows, x being a positive integer greater than or equal to 1;

the writing, by the voltage writing circuit, the display voltage into the second node in response to the enable level of the first scanning signal comprises: writing, by the voltage writing circuits in x circuit rows of the plurality of circuit rows, the display voltage into the second node in response to the enable level of the first scanning signal provided by a same first scanning signal line; and

the writing, by the voltage writing circuit, the node reset voltage into the second node in response to the enable level of the first scanning signal comprises: writing, by the voltage writing circuits in x circuit rows of the plurality of circuit rows, the node reset voltage into the second node in response to the enable level of the first scanning signal provided by the same first scanning signal line.

19. The method according to claim 13 , wherein

each of the plurality of pixel circuits further comprises a first reset circuit, and the first reset circuit is electrically connected between a first reset signal line and the first node; and

the method further comprises:

in the first non-light-emission period and in at least part of the second non-light-emission period, writing, by the first reset circuit, a first reset voltage into an anode of the light-emission element in response to an enable level of a third scanning signal.

20. The method according to claim 13 , wherein

each of the plurality of pixel circuits further comprises a second reset circuit, and the second reset circuit is electrically connected to a fourth scanning signal line, a second reset signal line, and the first node, respectively; and

the method further comprises:

in the first non-light-emission period, writing, by the second reset circuit, a second reset voltage into the first node in response to an enable level of a fourth scanning signal.

21. A display apparatus, comprising a display panel, wherein the display panel comprises a plurality of pixel circuits, and each of the plurality of pixel circuits comprises:

a drive transistor, comprising a gate electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node;

a voltage writing circuit, electrically connected to a first scanning signal line, a data line, and the second node, respectively; and

a threshold compensation circuit, electrically connected to a second scanning signal line, the third node, and the first node, respectively;

wherein a driving cycle of each of the plurality of the pixel circuits comprises a writing phase and at least one holding phase, the writing phase comprises a first non-light-emission period, and the at least one holding phase comprises a second non-light-emission period;

the voltage writing circuit is configured to write a display voltage into the second node in the first non-light-emission period in response to an enable level of a first scanning signal, and write a node reset voltage into the second node in at least part of the second non-light-emission period in response to the enable level of the first scanning signal; and

the threshold compensation circuit is configured to compensate for a threshold voltage of the drive transistor in the first non-light-emission period in response to an enable level of a second scanning signal;

the display panel further comprising a plurality of circuit rows arranged along a first direction,

wherein each circuit row of the plurality of circuit rows comprises pixel circuits arranged along a second direction, and the first direction intersects the second direction; and

wherein one first scanning signal line is electrically connected to voltage writing circuits of the pixel circuits in x circuit rows of the plurality of circuit rows, x being a positive integer greater than or equal to 1.