IP Library › Granted Patent US 11,749,322
Granted Patent B2
US 11,749,322 · App. 17/856,099 · Granted Sep 5, 2023

Copy data in a memory system with artificial intelligence mode

Inventor: Alberto Troia (Munich, DE)
Assignee: Micron Technology, Inc.
G11C7/22G06F11/1448G06F12/0246G06F18/214G06N3/08G11C11/409
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Quick Facts
Patent No.
US 11,749,322
App. No.
17/856,099
Granted
Sep 5, 2023
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.

Claims (46)

1. A method, comprising:

sending a command to copy data from a first memory device to a second memory device and to execute a training or inference operation on the second memory device,

wherein the command comprises a first address and a second address, the first address identifying the first memory device storing the data associated with the training or inference operation and the second address identifying the second memory device as a target for the data.

2. The method of claim 1 , further comprising sending the command when the first memory device and the second memory devices are performing artificial intelligence (AI) operations.

3. The method of claim 1 , further comprising receiving an additional command indicating that an apparatus comprising the first memory device and the second memory device operate in an artificial intelligence (AI) mode.

4. The method of claim 1 , further comprising receiving an additional command to perform artificial intelligence (AI) operations using an AI accelerator based on a status of each of a number of registers.

5. The method of claim 1 , further comprising performing another training or inference operation on the first memory device.

6. A system, comprising:

a number of memory devices coupled to a controller, wherein each of the number of memory devices is configured as part of a neural network and include a number of memory arrays; and

the controller configured to:

send a command to copy data from a first memory device of the number of memory devices to a second memory device of the number of memory devices,

wherein the first memory device and the second memory device are performing artificial intelligence (AI) operations using the data; and

execute a training or inference operation on the second memory device, wherein the command comprises a first address and a second address, the first address identifying the first memory device storing the data associated with the training or inference operation and the second address identifying the second memory device as a target for the data.

7. The system of claim 6 , wherein the copied data is neural network data.

8. The system of claim 6 , wherein the copied data is activation function data.

9. The system of claim 6 , further comprising the controller configured to copy the data from the first memory device to a third memory device of the number of memory devices in response to receiving another command that comprises the first address and a third address, the first address identifying the first memory device storing data for the training or inference operation and the third address identifying the third memory device as a target for the data.

10. The system of claim 9 , further comprising the controller configured to perform another training or inference operation on the third memory device using the data copied from the first memory device.

11. A system, comprising:

a number of memory devices coupled to a controller, wherein each of the number of memory devices is configured as part of a neural network;

a plurality of registers configured to define the neural network used during an artificial intelligence (AI) operation; and

the controller configured to:

receive a first command that comprises a first address and a second address, the first address identifying a first memory device storing data for a training or inference operation and the second address identifying a second memory device as a target for the data;

send a second command to the first memory device to:

read the data from a first memory array in the first memory device and transmit the data to a second memory array in the second memory device of the number of memory devices; and

perform the AI operation on the first memory device using the data.

12. The system of claim 11 , further comprising the controller configured to send a third command to the second memory device to:

receive the data and write the data to the second memory array in the second memory device; and

perform the AI operation on the second memory device using the data.

13. The system of claim 11 , wherein the plurality of registers configured to define the neural network comprises the plurality of registers configured to:

define a size of temporary banks used in the AI operation; and

define a start address and an end address of the temporary banks.

14. The system of claim 11 , further comprising the plurality of registers configured to enable a debug mode of an AI accelerator of the system.

15. The system of claim 11 , wherein the plurality of registers configured to define the neural network comprises the plurality of registers configured to define a size, a number, and a location of neurons of the neural network used during the AI operation or other AI operations.

16. The system of claim 11 , wherein the plurality of registers configured to define the neural network comprises the plurality of registers configured to define a size, a number, and a location of layers of the neural network used during the AI operation or other AI operations.

17. The system of claim 11 , wherein the plurality of registers configured to define the neural network comprises the plurality of registers configured to:

define a layer where a debug mode stops the AI operation;

change a content of the neural network;

observe an output of the layer; or

a combination thereof.

18. The system of claim 13 , wherein the plurality of registers configured to define the neural network comprises the plurality of registers configured to:

enable usage of an activation function for each neuron of the neural network;

enable usage of the activation function for each layer of the neural network; and

enable usage of an external activation function.

19. The system of claim 13 , wherein the plurality of registers configured to define the neural network comprises the plurality of registers configured to:

define a size of bias values used in the AI operation; and

define a number of bias values used in the AI operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2022
From: TROIA, ALBERTO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 060563/0148 →
Continuity (3)
Continuation 17328751 · May 24, 2021
Continuation 16554924 · Aug 29, 2019
Related Publication 20220399050A1 · Dec 15, 2022