Memory system

1. A memory system, comprising:

a normal memory area suitable for storing normal data;

a security memory area suitable for storing security data;

a first row hammering detection circuit suitable for sampling a portion of rows that are activated in the normal memory area and counting activation numbers of the sampled rows to select first rows to be refreshed among the sampled rows; and

a second row hammering detection circuit suitable for counting activation numbers of all rows in the security memory area to select second rows to be refreshed.

2. The memory system of claim 1 , further comprising:

different levels of cache memories,

wherein the second row hammering detection circuit stores a counting result corresponding to the rows activated in the security memory area in one cache memory among the different levels of the cache memories.

3. The memory system of claim 2 , further comprising:

the one cache memory used by the second row hammering detection circuit is a last-level cache memory among the different levels of the cache memories.

4. The memory system of claim 2 , wherein the normal memory area, the security memory area and the first row hammering detection circuit are included in a memory, and

the second row hammering detection circuit is included in a memory controller suitable for controlling the memory.

5. The memory system of claim 4 , wherein the different levels of the cache memories are included in a processor including the memory controller.

6. A memory system, comprising:

a normal memory area suitable for storing normal data;

a security memory area suitable for storing security data;

a first row hammering detection circuit suitable for sampling a portion of rows that are activated in the normal memory area and counting activation numbers of the sampled rows to select first rows to be refreshed;

a second row hammering detection circuit suitable for counting activation numbers of all rows in the security memory area to select second rows to be refreshed;

a cache memory suitable for storing an error correction code corresponding to the security data; and

an error correction circuit suitable for correcting an error of data that are read from the security memory area based on an error correction code stored in the cache memory.

7. The memory system of claim 6 , wherein the normal memory area, the security memory area, and the first row hammering detection circuit are included in a memory,

wherein the cache memory is included in a processor, and

wherein the processor includes a memory controller, and the second row hammering detection circuit is included in a memory controller.

8. The memory system of claim 7 , wherein the security memory area is allowed to be accessed, by the processor, only via the cache memory.

9. The memory system of claim 7 , wherein the second row hammering detection circuit stores a counting result corresponding to the rows activated in the security memory area in the cache memory.

10. The memory system of claim 7 , wherein the processor further includes a processor core suitable for processing instructions and accessing the memory via the cache memory.

11. The memory system of claim 10 , wherein the memory controller further includes:

a host interface suitable for communicating with a host;

a scheduler suitable for scheduling operations of the memory;

a command generator suitable for generating a command to be applied to the memory; and

a memory interface suitable for communicating with the memory.

12. A memory system, comprising:

a memory including:

a normal area suitable for storing normal data,

a security area suitable for storing security data, and

a first row hammering detection circuit suitable for counting activation numbers of rows of the normal area in a random-row counting manner to detect rows to be refreshed; and

a processor including:

a second row hammering detection circuit suitable for counting activation numbers of rows of the security area in a full-row counting manner to detect rows to be refreshed.

13. The memory system of claim 12 , wherein the processor further includes:

different levels of cache memories, and

wherein the second row hammering detection circuit stores a counting result corresponding to the rows activated in the security area in a last-level cache memory among the different levels of the cache memories.