Semiconductor manufacturing apparatus

1. A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, the method comprising:

determining whether a mounting processing is stopped during the mounting processing of the semiconductor chip or the stacked body;

evacuating, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the mounting processing is stopped;

determining whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and

returning the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.

2. The semiconductor manufacturing method according to claim 1 ,

wherein the determining whether the mounting processing is stopped includes determining whether an apparatus performing the mounting processing stops, and

wherein the evacuating the semiconductor chip or the stacked body includes evacuating the semiconductor chip or the stacked body when it is determined that the apparatus stops.

3. The semiconductor manufacturing method according to claim 1 ,

wherein the determining whether the mounting processing is stopped comprises

measuring a time elapsed after the support substrate on which the semiconductor chip or the stacked body is mounted has been transported onto a stage on which a mounting processing is performed or a time elapsed after the semiconductor chip or the stacked body has been mounted onto the stage, and

determining whether the elapsed time is not less than a first set time,

wherein the evacuating the semiconductor chip or the stacked body includes evacuating the semiconductor chip or the stacked body when it is determined that the elapsed time is not less than the first set time.

4. The semiconductor manufacturing method according to claim 3 , further comprising:

measuring a cumulative time for which the semiconductor chip or the stacked body has remained on the stage when it is determined that the mounting processing is resumed; and

determining whether the cumulative time is within a second set time,

wherein the continuing the mounting processing includes returning the semiconductor chip or the stacked body to a position before the evacuation and continuing the mounting processing when the cumulative time is within the second set time, and transporting the semiconductor chip or the stacked body out when the cumulative time exceeds the second set time.

5. The semiconductor manufacturing method according to claim 1 ,

wherein the determining whether the mounting processing is stopped comprises

measuring a time elapsed after the mounting processing has been stopped, and

determining whether the elapsed time is not less than a first set time,

wherein the evacuating the semiconductor chip or the stacked body includes evacuating the semiconductor chip or the stacked body when it is determined that the elapsed time is not less than the first set time.

6. The semiconductor manufacturing method according to claim 1 ,

wherein the semiconductor chip or the stacked body comprises a group of semiconductor chips comprising a plurality of stacked semiconductor chips,

wherein the method further comprises

detecting an amount of positional deviation between a mounting coordinate on a semiconductor chip stacked last among the plurality of stacked semiconductor chips and a reference coordinate on a semiconductor chip stacked immediately before the semiconductor chip stacked last, and

determining whether the amount of detected positional deviation is within a standard amount, and

wherein when it is determined that the mounting processing stops, the evacuating the semiconductor chip or the stacked body includes evacuating the group of semiconductor chips after detecting the amount of positional deviation, and when the amount of detected positional deviation exceeds the standard amount, evacuating the group of semiconductor chips.

7. The semiconductor manufacturing method according to claim 1 ,

wherein the semiconductor chip or the stacked body comprises a group of semiconductor chips comprising m (m is an integer of 2 or more) semiconductor chips stacked,

wherein the method further comprises,

detecting an amount of positional deviation between a reference coordinate on a semiconductor chip stacked on a n-th step (n is an integer of 1 or more and less than m) and a mounting coordinate on a semiconductor chip stacked on a m-th step among the m stacked semiconductor chips, and

determining whether the amount of detected positional deviation is within a standard amount, and

wherein when it is determined that the mounting processing stops, the evacuating the semiconductor chip or the stacked body includes evacuating the group of semiconductor chips after detecting the amount of positional deviation, and when the amount of detected positional deviation exceeds the standard amount, evacuating the group of semiconductor chips and performing a predetermined warning processing.

8. The semiconductor manufacturing method according to claim 7 ,

wherein the continuing the mounting processing comprises detecting an amount of transport deviation between the mounting coordinate on the semiconductor chip stacked on the m-th step before the evacuation and the mounting coordinate on the semiconductor chip stacked on the m-th step returned to a position before the evacuation after the evacuation, correcting the reference coordinate on the semiconductor chip stacked on the n-th step based on the amount of transport deviation, and while detecting the amount of positional deviation between the corrected reference coordinate and the mounting coordinate on semiconductor chips stacked on the (m+1)-th and subsequent steps, stacking semiconductor chips on the (m+1)-th and subsequent steps based on the corrected reference coordinate.

9. The semiconductor manufacturing method according to claim 1 ,

wherein the semiconductor chip or the stacked body comprises a group of semiconductor chips comprising m (m is an integer of 2 or more) semiconductor chips stacked,

wherein a support substrate that supports the lowermost semiconductor chip on the stage among the group of semiconductor chips or the stacked body or the lowermost semiconductor chip comprises a first reference index provided at a position that is visible from above the support substrate when stacking the group of semiconductor chips,

wherein the lowermost semiconductor chip comprises a second reference index provided at a position that is not visible from above the support substrate when stacking the group of semiconductor chips, and

wherein the method further comprises

detecting coordinates of the first reference index and the second reference index,

detecting an amount of positional deviation between a mounting coordinate on the semiconductor chip stacked on the m-th step and a reference coordinate based on the second reference index, and

determining whether the amount of detected positional deviation is within a standard amount, and

wherein when it is determined that the mounting processing stops, the evacuating the semiconductor chip or the stacked body includes evacuating the group of semiconductor chips after detecting the amount of positional deviation, and when the amount of detected positional deviation exceeds the standard amount evacuating the group of semiconductor chips.

10. The semiconductor manufacturing method according to claim 9 ,

wherein the detecting the amount of positional deviation comprises when continuing the mounting processing after the evacuation, detecting an amount of transport deviation between a position of the first reference index before evacuation and a position of the first reference index after returning to the original position after the evacuation, correcting the reference coordinate based on the amount of transport deviation, and detecting an amount of positional deviation between the corrected reference coordinate and the mounting coordinate on semiconductor chips stacked on the (m+1)-th and subsequent steps.