Array substrate mother board, array substrate, display panel and display device

1. An array substrate mother board, comprising:

a plurality of array substrates arranged in an array, wherein each array substrate of the plurality of array substrates comprise a first boundary extending along a first direction and a second boundary extending along a second direction, and the first direction intersects the second direction;

each array substrate comprises a component disposing area;

each array substrate further comprises a base substrate and a drive circuit layer, wherein the drive circuit layer comprises a gate metal layer and a first metal layer, the first metal layer is disposed on a side of the gate metal layer facing away from the base substrate, and the first metal layer comprises a plurality of capacitor plates arranged in an array along the first direction and along the second direction;

the plurality of array substrates comprises a plurality of first-type array substrates, and the plurality of first-type array substrates are arranged along the first direction and are adjacent to a boundary extending along the first direction in the array substrate mother board; and

among the plurality of first-type array substrates, along the second direction, two sides of the component disposing area comprise a first sub-area and a second sub-area, the first sub-area and the second sub-area each comprise a plurality of capacitor plates, and along the second direction, any two capacitor plates of the plurality of capacitor plates in the first sub-area and the second sub-area are not connected on the first metal layer.

2. The array substrate mother board of claim 1 , wherein the plurality of array substrates comprise a plurality of second-type array substrates, the plurality of second-type array substrates are arranged along the second direction and are adjacent to a boundary extending along the second direction and in the array substrate mother board;

among the plurality of second-type array substrates, along the first direction, two sides of the component disposing area comprise a third sub-area and a fourth sub-area, wherein the third sub-area and the fourth sub-area comprise a plurality of the capacitor plates, and along the first direction, any two capacitor plates of the plurality of the capacitor plates in the third sub-area and the fourth sub-area are not connected on the first metal layer.

3. The array substrate mother board of claim 1 , wherein in any one array substrate of the plurality of array substrates, among a plurality of capacitor plates respectively disposed on two sides of the component disposing area and along the second direction, any two capacitor plates are disposed on two sides of the component disposing area, are not connected on a plane where the first metal layer is located.

4. An array substrate, comprising:

a first boundary extending along a first direction and a second boundary extending along a second direction, wherein the first direction intersects the second direction;

the array substrate comprises a component disposing area;

the array substrate further comprises a base substrate and a drive circuit layer, wherein the drive circuit layer comprises a gate metal layer and a first metal layer, the first metal layer is disposed on a side of the gate metal layer facing away from the base substrate, and the first metal layer comprises a plurality of capacitor plates arranged in an array along the first direction and along the second direction; and

in the array substrate, along the second direction, two sides of the component disposing area comprise a first sub-area and a second sub-area, the first sub-area and the second sub-area each comprise a plurality of the capacitor plates, and along the second direction, any two capacitor plates of the plurality of the capacitor plates in the first sub-area and the second sub-area are not connected on the first metal layer.

5. The array substrate of claim 4 , wherein the any two capacitor plates arranged along the second direction are not connected on a plane where the first metal layer is located.

6. The array substrate of claim 5 , wherein the any two capacitor plates arranged along the second direction are disposed insulatedly.

7. The array substrate of claim 6 , wherein along the first direction and along the second direction, at the first metal layer, any two capacitor plates are disposed insulatedly.

8. The array substrate of claim 7 , wherein the drive circuit layer further comprises:

a second metal layer disposed on a side of the first metal layer facing away from the base substrate and a third metal layer on a side of the second metal layer facing away from the base substrate;

the second metal layer comprises a plurality of first power signal lines, the plurality of first power signal lines extend along the first direction, and the plurality of first power signal lines are arranged along the second direction; and

the third metal layer comprises a plurality of second power signal lines, the plurality of second power signal lines extend along the second direction, the plurality of second power signal lines are arranged along the first direction, and the plurality of second power signal lines and the plurality of second power signal lines are connected to a same power supply voltage signal input terminal.

9. The array substrate of claim 6 , wherein two adjacent capacitor plates arranged along the first direction are electrically connected.

10. The array substrate of claim 9 , wherein the drive circuit layer further comprises:

a fourth metal layer disposed on a side of the first metal layer facing away from the base substrate;

a plurality of capacitor plates of the fourth metal layer arranged along the first direction and electrically connected to each other are multiplexed as a third power signal line, and a plurality of third power signal lines are arranged along the second direction; and

the fourth metal layer comprises a plurality of fourth power signal lines, the plurality of fourth power signal lines extend along the second direction, the plurality of fourth power signal lines are arranged along the first direction, and the plurality of third power signal lines and the plurality of fourth power signal lines are connected to a same power supply voltage signal input terminal.

11. The array substrate of claim 10 , wherein a fourth power signal line comprises:

a wiring portion and a first connecting portion, wherein the wiring portion is disposed on the fourth metal layer, and the first connecting portion is disposed on the first metal layer; and

the wiring portion extends along the second direction, and two adjacent wiring portions along the second direction are electrically connected through the first connecting portion.

12. The array substrate of claim 10 , wherein the drive circuit layer further comprises:

an initialization signal line, the initialization signal line extends along the second direction, and a plurality of initialization signal lines are arranged along the first direction; and

the initialization signal line is disposed on the gate metal layer.

13. The array substrate of claim 5 , wherein the drive circuit layer further comprises:

a connecting metal layer disposed between the base substrate and the first metal layer, and the connecting metal layer is provided with a second connecting portion; and

any two adjacent capacitor plates arranged along the second direction are electrically connected through the second connecting portion, and the any two adjacent capacitor plates are connected to a power supply voltage signal input terminal.

14. The array substrate of claim 13 , wherein the gate metal layer is multiplexed as the connecting metal layer.

15. The array substrate of claim 14 , wherein two adjacent capacitor plates arranged along the first direction are electrically connected, a plurality of capacitor plates arranged along the first direction and electrically connected to each other are multiplexed as third power signal lines, and a plurality of third power signal lines are arranged along the second direction; and

a plurality of capacitor plates arranged along the second direction and electrically connected to each other are multiplexed as fifth power signal lines, a plurality of fifth power signal lines are arranged along the second direction, and the plurality of third power signal lines and the plurality of fifth power signal lines are connected to a same power supply voltage signal input terminal.

16. The array substrate of claim 15 , wherein the drive circuit layer further comprises:

an initialization signal line, the initialization signal line extends along the second direction, and a plurality of initialization signal lines are arranged along the first direction; and

the initialization signal line is disposed on the gate metal layer.

17. The array substrate of claim 13 , wherein the drive circuit layer further comprises:

a fifth metal layer disposed on a side of the first metal layer facing away from the base substrate;

a plurality of the capacitor plates of the fifth metal layer arranged along the second direction and electrically connected to each other are multiplexed as a fifth power signal line, and a plurality of fifth power signal lines are arranged along the first direction; and

the fifth metal layer comprises a plurality of sixth power signal lines, the plurality of sixth power signal lines extend along the first direction, the plurality of sixth power signal lines are arranged along the second direction, and the plurality of fifth power signal lines and the plurality of sixth power signal lines are connected to a same power supply voltage signal input terminal.

18. The array substrate of claim 17 , wherein the drive circuit layer further comprises:

an initialization signal line, the initialization signal line extends along the second direction, and a plurality of initialization signal lines are arranged along the first direction; and

the initialization signal line is disposed on the first metal layer.

19. A display panel, comprising an array substrate, wherein the array substrate comprises:

a first boundary extending along a first direction and a second boundary extending along a second direction, wherein the first direction intersects the second direction;

the array substrate comprises a component disposing area;

the array substrate further comprises a base substrate and a drive circuit layer, wherein the drive circuit layer comprises a gate metal layer and a first metal layer, the first metal layer is disposed on a side of the gate metal layer facing away from the base substrate, and the first metal layer comprises a plurality of capacitor plates arranged in an array along the first direction and along the second direction; and

in the array substrate, along the second direction, two sides of the component disposing area comprise a first sub-area and a second sub-area, the first sub-area and the second sub-area each comprise a plurality of the capacitor plates, and along the second direction, any two capacitor plates of the plurality of the capacitor plates in the first sub-area and the second sub-area are not connected on the first metal layer.

20. A display device, comprising:

comprising the display panel of claim 19 ,

and further comprising an imaging component, in a direction perpendicular to a plane where the display panel is located, the imaging component at least partially overlaps the component disposing area.