IP Library › Granted Patent US 11,749,730
Granted Patent B2
US 11,749,730 · App. 17/347,136 · Granted Sep 5, 2023

Semiconductor device with contact structure and method for preparing the same

Inventor: Tse-Yao Huang (Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L29/41775H01L23/53271H01L29/401H01L29/41725H01L29/45H01L29/456H01L29/458H01L29/7839H01L29/806
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Quick Facts
Patent No.
US 11,749,730
App. No.
17/347,136
Granted
Sep 5, 2023
Kind
B2
Abstract

The present disclosure relates to a semiconductor device with a contact structure and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, and a dielectric layer disposed over the source/drain structure. The semiconductor device also includes a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device further includes a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer.

Claims (18)

1. A semiconductor device, comprising:

a source/drain structure disposed over a semiconductor substrate;

a dielectric layer disposed over the source/drain structure;

a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer, wherein the polysilicon stack comprises a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer, the first polysilicon layer is undoped, and the second polysilicon layer is doped; and

a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer;

wherein the second polysilicon layer is in direct contact with the dielectric layer.

2. The semiconductor device of claim 1 , wherein the second polysilicon layer is doped with arsenic (As), boron (B), or phosphorous (P).

3. The semiconductor device of claim 1 , wherein the polysilicon stack further comprises:

a third polysilicon layer disposed over the second polysilicon layer, wherein the third polysilicon layer is undoped; and

a fourth polysilicon layer disposed over the third polysilicon layer, wherein the fourth polysilicon layer is doped.

4. The semiconductor device of claim 3 , wherein a dopant concentration of the second polysilicon layer is greater than a dopant concentration of the fourth polysilicon layer.

5. The semiconductor device of claim 1 , wherein the contact structure comprises a barrier layer and a conductive layer disposed over and surrounded by the barrier layer, and wherein the barrier layer includes titanium (Ti), titanium nitride (TiN), or a combination thereof, and the conductive layer includes tungsten (W).

6. The semiconductor device of claim 1 , wherein the source/drain structure includes an epitaxial layer and a silicide layer disposed over the epitaxial layer.

7. The semiconductor device of claim 6 , wherein the silicide layer includes cobalt silicide.

8. The semiconductor device of claim 6 , further comprising:

a gate structure penetrating through the dielectric layer, the silicide layer, and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate, and the gate structure is adjacent to the polysilicon stack and the contact structure.

9. The semiconductor device of claim 6 , further comprising:

a gate structure penetrating through the dielectric layer and the epitaxial layer, wherein the gate structure extends into the semiconductor substrate, and the gate structure is separated from the silicide layer by the dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: HUANG, TSE-YAO
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 056671/0426 →
Continuity (1)
Related Publication 20220399446A1 · Dec 15, 2022
Cited By (3)
US 12,506,029 US 12,538,788 US 12,666,955