IP Library › Granted Patent US 11,749,740
Granted Patent B2
US 11,749,740 · App. 16/731,058 · Granted Sep 5, 2023

High electron mobility transistor and method for fabricating the same

Inventors: Bo-Rong Chen (Hsinchu County, TW); Che-Hung Huang (Hsinchu, TW); Chun-Ming Chang (Kaohsiung, TW); Yi-Shan Hsu (Taipei, TW); Chih-Tung Yeh (Taoyuan, TW); Shin-Chuan Huang (Tainan, TW); Wen-Jung Liao (Hsinchu, TW); Chun-Liang Hou (Hsinchu County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/66462H01L29/2003H01L29/7783
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Quick Facts
Patent No.
US 11,749,740
App. No.
16/731,058
Granted
Sep 5, 2023
Kind
B2
Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

Claims (10)

1. A high electron mobility transistor (HEMT), comprising:

a buffer layer on a substrate;

a first barrier layer on the buffer layer;

a p-type semiconductor layer on the first barrier layer;

a spacer adjacent to the p-type semiconductor layer, wherein the spacer is made of a dielectric material, a bottom surface of the spacer is even with a bottom surface of the p-type semiconductor layer, the spacer comprises an inner sidewall and an outer sidewall, and the outer sidewall of the spacer comprises a curve;

a second barrier layer adjacent to the spacer on the first barrier layer, wherein a topmost surface of the second barrier layer is lower than a top surface of the p-type semiconductor layer;

a gate electrode on and directly contacting the p-type semiconductor layer, wherein a width of the gate electrode is less than a width of the p-type semiconductor layer;

a hard mask on the p-type semiconductor layer and laterally around the gate electrode, wherein a bottom surface of the hard mask is even with a bottom surface of the gate electrode, a top surface of the hard mask is lower than a top surface of the gate electrode, and a topmost point of the spacer is at the same level with the top surface of the hard mask and lower than the top surface of the gate electrode; and

a source electrode and a drain electrode adjacent to two sides of the spacer.

2. The HEMT of claim 1 , wherein the hard mask comprises a dielectric material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2019
From: CHEN, BO-RONG; HUANG, CHE-HUNG; CHANG, CHUN-MING; HSU, YI-SHAN; YEH, CHIH-TUNG; HUANG, SHIN-CHUAN; LIAO, WEN-JUNG; HOU, CHUN-LIANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 051390/0413 →
Priority Claims (1)
CN 201911241221.7 · Dec 6, 2019 · national
Continuity (1)
Related Publication 20210175343A1 · Jun 10, 2021