Solid-state imaging element, imaging apparatus, and control method of solid-state imaging element with improved reading speed of pixel signals
It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.
1. A device comprising:
a plurality of pixels arranged in rows and columns;
a plurality of column lines, each of the plurality of column lines being coupled to a respective column of pixels of the plurality of pixels; and
circuitry comprising a plurality of analog-to-digital converters, at least one of the plurality of analog-to-digital converters being coupled to at least two column lines of the plurality of column lines,
wherein the at least one of the plurality of analog-to-digital converters comprises a comparator configured to compare a reference signal with a pixel signal provided to the comparator through one of the at least two column lines, and
wherein the comparator comprises:
a first transistor configured to receive, at a gate terminal thereof, a first pixel signal provided through a first column line of the at least two column lines;
a second transistor configured to receive, at a gate terminal thereof, a second pixel signal provided through a second column line of the at least two column lines; and
a third transistor configured to receive, at a gate terminal thereof, the reference signal,
wherein the at least one of the plurality of analog-to-digital converters comprises successive approximation register logic circuitry coupled to the comparator.
2. The device of claim 1 , wherein each of the plurality of analog-to-digital converters is coupled to at least two respective column lines of the plurality of column lines.
3. The device of claim 1 , wherein the circuitry is configured to drive at least two rows of pixels of the plurality of pixels simultaneously.
4. The device of claim 1 , wherein the circuitry is configured to vary the reference signal over time.
5. The device of claim 4 , wherein the circuitry is configured to vary, during a predefined time slot, the reference signal until a least significant bit (LSB) is generated based on the pixel signal.
6. The device of claim 1 , wherein the comparator further comprises:
a first switch coupled to a source and a drain of the first transistor;
a second switch coupled to a source and a drain of the second transistor;
a third switch coupled to the first switch; and
a fourth switch coupled to the second switch.
7. The device of claim 6 , wherein the first switch is configured to receive a first control signal and the third switch is configured to receive an inversion signal of the first control signal; and wherein the second switch is configured to receive a second control signal and the fourth switch is configured to receive an inversion signal of the second control signal.
8. The device of claim 1 , wherein the plurality of analog-to-digital converters comprises a first analog-to-digital converter and a second analog-to-digital converter, and wherein the circuitry is configured to provide a first reference signal to the first analog-to-digital converter and a second reference signal to the second analog-to-digital converter, the second reference signal being different from the first reference signal.
9. The device of claim 1 , wherein the device is mounted on a vehicle.
10. A device comprising:
a pixel area comprising a plurality of pixel lines comprising:
a first pixel line coupled to a first plurality of pixels and a second pixel line coupled to a second plurality of pixels; and
circuitry comprising an analog-to-digital converter coupled to the first pixel line and to the second pixel line,
wherein the analog-to-digital converter comprises a comparator configured to compare a reference signal with a pixel signal provided to the comparator through one of the first pixel line and the second pixel line, and
wherein the comparator comprises:
a first transistor configured to receive, at a gate terminal thereof, a first pixel signal provided through the first pixel line;
a second transistor configured to receive, at a gate terminal thereof, a second pixel signal provided through the second pixel line; and
a third transistor configured to receive, at a gate terminal thereof, the reference signal wherein the analog-to-digital converter comprises successive approximation register logic circuitry coupled to the comparator.
11. The device of claim 10 , wherein the circuitry is configured to drive at least two rows of pixels of the pixel area simultaneously.
12. The device of claim 10 , wherein the circuitry is configured to vary the reference signal over time.
13. The device of claim 12 , wherein the circuitry is configured to vary, during a predefined time slot, the reference signal until a least significant bit (LSB) is generated based on the pixel signal.
14. The device of claim 10 , wherein the comparator further comprises:
a first switch coupled to a source and a drain of the first transistor;
a second switch coupled to a source and a drain of the second transistor;
a third switch coupled to the first switch; and
a fourth switch coupled to the second switch.
15. The device of claim 14 , wherein the first switch is configured to receive a first control signal and the third switch is configured to receive an inversion signal of the first control signal; and wherein the second switch is configured to receive a second control signal and the fourth switch is configured to receive an inversion signal of the second control signal.
16. The device of claim 10 , wherein the analog-to-digital converter comprises a first analog-to-digital converter and a second analog-to-digital converter, and wherein the circuitry is configured to provide a first reference signal to the first analog-to-digital converter and a second reference signal to the second analog-to-digital converter, the second reference signal being different from the first reference signal.
17. The device of claim 10 , wherein the device is mounted on a vehicle.