Semiconductor device and method fabricating the same

1. A method for fabricating a semiconductor device, the method comprising:

providing a substrate having an etch stop layer formed thereon;

forming a preliminary stacked structure on the etch stop layer, the preliminary stacked structure including a lower sacrifice layer contacting the etch stop layer, a support layer, and an upper sacrifice layer;

forming a hole penetrating the preliminary stacked structure and the etch stop layer;

forming a conductive pattern in the hole;

removing the upper sacrifice layer and a portion of the support layer;

removing the lower sacrifice layer;

forming a first conductive layer covering the conductive pattern; and

forming a dielectric layer covering the first conductive layer, a remaining portion of the support layer, and the etch stop layer.

2. The method of claim 1 , wherein the conductive pattern extends vertically from the substrate.

3. The method of claim 1 , wherein the remaining portion of the support layer extends horizontally from an outer sidewall of the conductive pattern.

4. The method of claim 1 , further comprising forming a second conductive layer covering the dielectric layer.

5. The method of claim 1 , wherein forming the conductive pattern comprises:

performing a deposition process comprising atomic layer deposition (ALD), chemical vapor deposition (CVD), or a sequential flow deposition (SFD) to form an electrode layer; and

performing a planarization process comprising etch-back or chemical mechanical polishing (CMP) to remove a portion of the electrode layer and expose a top surface of the preliminary stacked structure.

6. The method of claim 5 , wherein removing the upper sacrifice layer and the portion of the support layer comprises:

performing a wet etch process to remove the upper sacrifice layer; and

performing a dry etch process to remove the portion of the support layer.

7. The method of claim 1 , wherein forming the first conductive layer comprises selectively depositing the first conductive layer on an exposed surface of the conductive pattern by a deposition process including atomic layer deposition (ALD), chemical vapor deposition (CVD), or a sequential flow deposition (SFD).

8. The method of claim 1 , wherein a combination of the conductive pattern and the first conductive layer serves as a lower electrode for a capacitor in DRAM, and a resistivity of the lower electrode is up to 150 microohm centimeter (μΩ·cm).