Transistor display panel including lower electrode disposed under a semiconductor and display device including the same
A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.
1. A transistor display panel comprising:
a substrate;
a lower electrode disposed on the substrate;
a buffer layer covering the lower electrode;
a transistor disposed on the substrate; and
a pixel electrode connected to the transistor,
wherein the transistor includes:
a semiconductor on the substrate,
a first insulating layer disposed on the semiconductor,
a gate electrode on the first insulating layer overlapping the semiconductor,
a second insulating layer covering the gate electrode, and
a source electrode and a drain electrode disposed on the second insulating layer,
wherein the lower electrode is disposed under the semiconductor and is electrically connected to the pixel electrode,
wherein the semiconductor includes a channel, and a source region and a drain region disposed at respective sides of the channel, and
wherein the source region and the drain region are respectively connected to the source electrode and the drain electrode.
2. The transistor display panel of claim 1 , wherein the gate electrode includes a main gate layer, and an upper gate layer and a lower gate layer respectively disposed on and under the main gate layer.
3. The transistor display panel of claim 2 , wherein the source electrode includes a main source layer and a lower source layer disposed thereunder, and the drain electrode includes a main drain layer and a lower drain layer disposed thereunder.
4. The transistor display panel of claim 1 , wherein the pixel electrode is connected to the source electrode.
5. The transistor display panel of claim 1 , further comprising:
a light-emitting diode element connected to the transistor and comprising the pixel electrode, an emission layer, and a common electrode.
6. The transistor display panel of claim 1 , further comprising:
a scan line disposed on the substrate;
a data line crossing the scan line; and
a second transistor connected to the scan line and the data line,
wherein the second transistor includes a second semiconductor disposed on a same layer as the semiconductor, and a second gate electrode overlapping the second semiconductor.
7. The transistor display panel of claim 6 , wherein the second gate electrode includes at least three layers.
8. The transistor display panel of claim 6 , wherein the semiconductor and the second semiconductor include an oxide semiconductor material.
9. The transistor display panel of claim 1 , wherein the lower electrode includes a metal having at least one among copper (Cu), copper alloys, aluminum (Al), aluminum alloys, molybdenum (Mo) and molybdenum alloys.
10. The transistor display panel of claim 9 , wherein the gate electrode includes a metal layer having at least one of molybdenum (Mo) and titanium (Ti).
11. The transistor display panel of claim 10 , wherein the pixel electrode includes a transparent conductive material having an indium tin oxide (ITO).
12. The transistor display panel of claim 1 , further comprising:
a storage capacitor connected to the gate electrode,
wherein one electrode of the storage capacitor is disposed on a same layer as the gate electrode.
13. The transistor display panel of claim 12 , wherein the one electrode of the storage capacitor and the gate electrode are formed as one body.
14. The transistor display panel of claim 12 , wherein the one electrode of the storage capacitor is extended from the gate electrode.
15. A display device comprising:
a substrate;
a lower electrode disposed on the substrate;
a buffer layer covering the lower electrode;
a semiconductor disposed on the buffer layer;
a first insulating layer disposed on the semiconductor;
a gate electrode disposed on the first insulating layer;
a second insulating layer covering the gate electrode;
a first electrode and a second electrode disposed on the second insulating layer and respectively connected to a first region and a second region of the semiconductor; and
a pixel electrode connected to the first electrode,
wherein the lower electrode is electrically connected to the first electrode and the pixel electrode, and
wherein the lower electrode is disposed between the substrate and the semiconductor.
16. The display device of claim 15 , wherein the first electrode is connected to the lower electrode through an opening of the buffer layer, the first insulating layer, and the second insulating layer.
17. The display device of claim 15 , further comprising:
an emission layer disposed on the pixel electrode, and
a common electrode disposed on the emission layer.
18. The display device of claim 15 , further comprising:
a scan line disposed on the substrate;
a data line crossing the scan line; and
a second transistor connected to the scan line and the data line,
wherein the second transistor includes:
a second semiconductor disposed on a same layer as the semiconductor,
a second gate electrode overlapping the second semiconductor, and
a second source electrode and a second drain electrode disposed on the same layer as the first electrode and the second electrode.
19. The display device of claim 15 , wherein the lower electrode overlaps at least a part of a channel of the semiconductor in a plan view.