Cache line coherence state downgrade

1. A method, comprising:

for a memory access class, detecting at least a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state;

in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state;

detecting a reset event for the memory access class; and

in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory access class as coherence state agnostic requests.

2. The method of claim 1 , further comprising:

maintaining a count of a number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state.

3. The method of claim 2 , further comprising:

in response to the reset event, resetting the count to zero.

4. The method of claim 1 , wherein the reset event includes detecting that a cache line in an exclusive state is converted to a cache line in a shared state, for the memory access class.

5. The method of claim 1 , further comprising:

storing cache lines into the cache in an exclusive state in response to one or more of load instructions and prefetch operations.

6. The method of claim 1 , wherein the memory access class is defined as a combination of memory access type and thread identifier.

7. The method of claim 1 , wherein treating the first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state comprises, in response to a coherence state agnostic request to insert a cache line into the cache, storing the cache line in the cache in a shared state.

8. The method of claim 1 , further comprising, for different memory access classes, tracking different numbers of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state.

9. The method of claim 8 , further comprising for multiple different memory access classes, independently responding to requests for cache lines according to the number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state.

10. A system, comprising:

a cache; and

a cache controller configured to:

for a memory access class, detect at least a threshold number of instances in which cache lines in an exclusive state in the cache are changed to an invalid state or a shared state without being in a modified state;

in response to the detecting, treat first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state;

detect a reset event for the memory access class; and

in response to detecting the reset event, treat second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.

11. The system of claim 10 , wherein the cache controller is further configured to:

maintain a count of a number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state.

12. The system of claim 11 , wherein the cache controller is further configured to:

in response to the reset event, reset the count to zero.

13. The system of claim 10 , wherein the reset event includes detecting that a cache line in an exclusive state is converted to a cache line in a shared state, for the memory access class.

14. The system of claim 10 , wherein the cache controller is further configured to:

store cache lines into the cache in an exclusive state in response to one or more of load instructions and prefetch operations.

15. The system of claim 10 , wherein the memory access class is defined as a combination of memory access type and thread identifier.

16. The system of claim 10 , wherein treating the first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state comprises, in response to a coherence state agnostic request to insert a cache line into the cache, storing the cache line in the cache in a shared state.

17. The system of claim 10 , wherein the cache controller is further configured to, for different memory access classes, track different numbers of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state.

18. The system of claim 17 , wherein the cache controller is further configured to, for multiple different memory access classes, independently respond to requests for cache lines according to the number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state.

19. A system, comprising:

a processor;

a cache; and

a cache controller configured to:

for a memory access class, detect at least a threshold number of instances in which cache lines in an exclusive state in the cache are changed to an invalid state or a shared state without being in a modified state;

in response to the detecting, treat first coherence state agnostic requests for the processor for cache lines for the memory access class as requests for cache lines in a shared state;

detect a reset event for the memory access class; and

in response to detecting the reset event, treat second coherence state agnostic requests for the processor for cache lines for the memory class as coherence state agnostic requests.

20. The system of claim 19 , wherein the cache controller is further configured to:

maintain a count of a number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state.