Folded memory modules

1. A memory controller for controlling a set of memory modules, the memory controller comprising:

a command/address interface to communicate commands and addresses to at least a first memory module and a second memory module;

a data interface including at least a first subset of memory controller data pins to communicate data with the first memory module and at least a second subset of memory controller data pins to communicate data with the second memory module;

a select interface to select between a first rank of memory devices and a second rank of memory devices,

wherein the first rank of memory devices includes at least one memory device of the first memory module coupled to the first subset of the memory controller data pins and at least one memory device of the second memory module coupled to the second subset of the memory controller data pins; and

wherein the second rank of memory devices including at least one memory device of the first memory module coupled to the first subset of the memory controller data pins and at least one memory device of the second memory module coupled to second subset of the memory controller data pins; and

configuration control logic to control a connectivity configuration of at least the first memory module by controlling which memory module data pins of the first memory module are enabled for communicating with the memory controller.

2. The memory controller of claim 1 , wherein the configuration control logic controls selection between a plurality of selectable data width configurations including at least a first half-width configuration in which a first subset of the memory module data pins are enabled and a second subset of the memory module data pins are disabled and a second half-width configuration in which the first subset of the memory module data pins are disabled and the second subset of the memory module data pins are enabled.

3. The memory controller of claim 2 , wherein the plurality of selectable data width configurations further includes a full-width configuration in which both the first subset and the second subset of the memory module data pins are enabled.

4. The memory controller of claim 2 , wherein the plurality of selectable data width configurations further includes a quarter-width configuration in which a quarter of the memory module data pins are enabled and remaining memory module data pins are disabled.

5. The memory controller of claim 1 , further including:

a control interface comprising a set of control pins to send the control signal to respective programmable registers of the first memory module to set the connectivity configuration.

6. The memory controller of claim 1 , wherein the configuration control logic is configured to output the connectivity configuration as a command sent over the command/address interface.

7. The memory controller of claim 1 , wherein the first rank of memory devices includes at least two memory devices of the first memory module and at least two memory devices of the second memory module, and wherein the second rank of memory devices includes at least two memory devices of the first memory module and at least two memory devices of the second memory module.

8. A method for controlling a set of memory modules by a memory controller, the method comprising:

sending a control signal to control a connectivity configuration of at least a first memory module by controlling which memory module data pins of the first memory module are enabled for communicating with the memory controller;

selecting, via a select interface of the memory controller, a first rank of memory devices that includes at least a first memory device of the first memory module and at least a second memory device of a second memory module;

communicating at least a first command and address associated with a first memory operation to the first rank of memory devices via a command/address interface;

while the first rank is selected, communicating data with at least the first memory module using a first subset of memory controller data pins and communicating data with at least the second memory module using a second subset of memory controller data pins to facilitate the first memory operation with respect to the first rank;

selecting, via the select interface of the memory controller, a second rank of memory devices that includes at least a third memory device of the first memory module and at least a fourth memory device of the second memory module;

communicating at least a second command and address associated with a second memory operation to the second rank of memory devices via the command/address interface; and

while the second rank is selected, communicating data with at least the first memory module using the first subset of memory controller data pins and communicating data with at least the second memory module using the second subset of memory controller data pins to facilitate the second memory operation with respect to the second rank.

9. The method of claim 8 , wherein sending the control signal comprises:

sending the control signal to select between a plurality of selectable configurations including at least a first half-width configuration in which a first subset of the memory module data pins are enabled and a second subset of the memory module data pins are disabled, and a second half-width configuration in which the first subset of the memory module data pins are disabled and the second subset of the memory data pins are enabled.

10. The method of claim 9 , wherein the plurality of selectable configurations further includes a full-width configuration in which both the first subset and the second subset of the memory module data pins are enabled.

11. The method of claim 8 , wherein sending the control signal comprises:

sending the control signal over a control interface separate from the command/address interface.

12. The method of claim 8 , wherein sending the control signal comprises:

sending the control signal over the command/address interface.

13. A memory controller comprising:

configuring means for sending a control signal to control a connectivity configuration of at least a first memory module by controlling which memory module data pins of the first memory module are enabled for communicating with the memory controller;

first selecting means for selecting between at least a first rank of memory devices and a second rank of memory devices, wherein the first rank includes at least a first memory device of the first memory module and at least a second memory device of a second memory module, and wherein the second rank includes at least a third memory device of the first memory module and at least a fourth memory device of the second memory module;

command/address communicating means for communicating at least a first command and address associated with a first memory operation to the first rank of memory devices via a command/address interface, and communicating at least a second command and address associated with a second memory operation to the second rank of memory devices via the command/address interface; and

data communicating means for communicating data with at least the first memory module using a first subset of memory controller data pins and communicating data with at least the second memory module using a second subset of memory controller data pins to facilitate the first memory operation with respect to the first rank while the first rank is selected, and for communicating data with at least the first memory module using the first subset of memory controller data pins and communicating data with at least the second memory module using the second subset of memory controller data pins to facilitate the second memory operation with respect to the second rank while the second rank is selected.

14. The memory controller of claim 13 , wherein the control signal selects between a plurality of selectable configurations including at least a first half-width configuration in which a first subset of the memory module data pins are enabled and a second subset of the memory module data pins are disabled, and a second half-width configuration in which the first subset of the memory module data pins are disabled and the second subset of the memory data pins are enabled.

15. The memory controller of claim 14 , wherein the plurality of selectable configurations further includes a full-width configuration in which both the first subset and the second subset of the memory module data pins are enabled.

16. The memory controller of claim 13 , wherein the configuring means is further for sending the control signal over a control interface separate from the command/address interface.

17. The memory controller of claim 13 , wherein the configuring means is further for sending the control signal over the command/address interface.