Method for manufacturing metal oxide semiconductor transistor

1. A method for manufacturing a metal oxide semiconductor transistor, comprising:

sequentially forming a gate stack structure and a hardmask layer on the gate stack structure on a substrate;

forming a first spacer on a sidewall of the gate stack structure and a sidewall of the hardmask layer;

forming a photoresist layer on a sidewall of the first spacer, wherein a top surface of the photoresist layer is higher than a top surface of the gate stack structure and the top surface of the photoresist layer is lower than a top surface of the first spacer;

removing the hardmask layer and a portion of the first spacer to expose the top surface of the gate stack structure with an etching process having a higher etching selectivity for the hardmask layer and the first spacer than an etching selectivity for the photoresist layer, wherein a top surface of a remaining first spacer is higher than the top surface of the gate stack structure;

removing the photoresist layer; and

forming a second spacer on a sidewall of the remaining first spacer, wherein a top surface of the second spacer is higher than the top surface of the gate stack structure;

wherein before forming the photoresist layer on the sidewall of the first spacer, the method further comprises: forming a first doped region in the substrate, wherein the first doped region is adjacent to the sidewall of the first spacer; and

wherein after forming the second spacer on the sidewall of the remaining first spacer, the method further comprises: forming a second doped region in the substrate, wherein the second doped region is adjacent to a sidewall of the second spacer.

2. The method according to claim 1 , wherein the first doped region is a lightly doped drain region.

3. The method according to claim 1 , wherein forming the photoresist layer comprises:

forming a photoresist material layer on the substrate to cover the substrate, the first spacer, and the hardmask layer; and

removing a portion of the photoresist material layer to expose a top surface of the hardmask layer and a portion of the sidewall of the first spacer and form the photoresist layer.

4. The method according to claim 3 , wherein a material of the photoresist material layer comprises a carbon-based material or a polymer material.

5. The method according to claim 1 , wherein a material of the hardmask layer comprises silicon oxide or silicon oxynitride.

6. The method according to claim 1 , wherein a material of the first spacer comprises silicon oxide, silicon nitride, or silicon oxynitride.

7. The method according to claim 1 , wherein the first spacer comprises:

a first sub-spacer, formed on the sidewall of the gate stack structure; and

a second sub-spacer, formed on a sidewall of the first sub-spacer.

8. The method according to claim 7 , wherein a material of the first sub-spacer comprises silicon oxide or silicon oxynitride.

9. The method according to claim 7 , wherein a material of the second sub-spacer comprises silicon nitride.

10. The method according to claim 1 , wherein forming the second spacer comprises:

conformally forming a spacer material layer on the substrate, the first spacer, and the gate stack structure by performing an atomic layer deposition (ALD) process or a plasma enhanced ALD process; and

removing a portion of the spacer material layer to expose the top surface of the gate stack structure.

11. The method according to claim 1 , wherein a material of the second spacer comprises silicon nitride.

12. The method according to claim 1 , wherein the second doped region is a source/drain region.