Backside contact to improve thermal dissipation away from semiconductor devices

1. A three-dimensional (3D) integrated circuit (IC) stack comprising:

a first IC die comprising a first semiconductor substrate, a first interconnect structure, and a first bonding structure arranged over the first interconnect structure;

a second IC die comprising a second semiconductor substrate, a second interconnect structure, and a second bonding structure arranged on the second semiconductor substrate, wherein the second bonding structure faces the first bonding structure;

a first backside contact extending from the second bonding structure to the second semiconductor substrate and being thermally coupled to at least one of the first interconnect structure or the second interconnect structure; and

a through substrate via (TSV) extending through the second semiconductor substrate, wherein the TSV is laterally spaced apart from the first backside contact, and wherein the TSV is not electrically coupled to the first backside contact.

2. The 3D IC stack of claim 1 , wherein a topmost surface of the first backside contact is arranged below a topmost surface of the TSV, wherein a bottommost surface of the TSV is arranged below the bottommost surface of the first backside contact.

3. The 3D IC stack of claim 1 , wherein the second IC die comprises a second semiconductor device arranged on the second semiconductor substrate, and wherein the first backside contact directly overlies the second semiconductor device.

4. The 3D IC stack of claim 1 , wherein the first backside contact comprises tungsten, and wherein the first and second interconnect structures comprise copper.

5. The 3D IC stack of claim 1 further comprising:

a third IC die comprising a third semiconductor substrate, a third interconnect structure arranged on a frontside of the third semiconductor substrate, and a third bonding structure arranged on the third interconnect structure, wherein the third bonding structure is arranged between the third semiconductor substrate and the second semiconductor substrate.

6. The 3D IC stack of claim 1 , wherein the first backside contact has a higher thermal conductivity than the TSV.

7. An integrated circuit (IC) die comprising:

a semiconductor substrate;

an interconnect structure arranged on the semiconductor substrate, and comprising interconnect vias and interconnect wires embedded within dielectric layers;

a first bonding structure arranged on the interconnect structure;

a second bonding structure arranged beneath the semiconductor substrate and comprising bonding wire layers and bonding vias within a bonding dielectric structure;

a contact arranged within the second bonding structure and coupled to the bonding wire layers and the bonding vias of the second bonding structure, wherein a first surface of the contact is thermally coupled to the semiconductor substrate, wherein a second surface of the contact is arranged below a bottommost surface of the semiconductor substrate; and

a through substrate via (TSV) extending through the semiconductor substrate and from the second bonding structure to the interconnect structure, wherein a topmost surface of the TSV is above the topmost surface of the contact.

8. The IC die of claim 7 , wherein the TSV is not electrically coupled to the contact.

9. The IC die of claim 8 , wherein the contact has a higher thermal conductivity than the TSV.

10. The IC die of claim 7 , wherein the contact and the TSV are coupled to a bond pad arranged within a third bonding structure bonded to the second bonding structure.

11. The IC die of claim 10 , wherein the bond pad comprises aluminum.

12. The IC die of claim 7 , wherein the contact has a higher thermal conductivity than the TSV.

13. The IC die of claim 7 , wherein the TSV comprises copper and the contact comprises tungsten.

14. The IC die of claim 7 , further comprising:

a glue layer separating the contact from the semiconductor substrate.

15. The IC die of claim 7 further comprising:

an additional contact arranged within the second bonding structure and coupled to the bonding wire layers and the bonding vias of the second bonding structure, wherein the additional contact is spaced apart from the contact by the semiconductor substrate.

16. A method of forming an integrated circuit, the method comprising:

depositing a first insulating layer over a first side of a semiconductor substrate;

forming a first opening in the first insulating layer to expose a portion of the first side of the semiconductor substrate;

forming a contact in the first opening;

depositing a second insulating layer over the first insulating layer and over the contact;

forming a second opening that extends completely through the first insulating layer, the second insulating layer, and the semiconductor substrate;

forming a through substrate via (TSV) in the second opening; and

forming additional insulating layers, bonding vias, and bonding wire layers over the second insulating layer to form a second bonding structure on the first side of the semiconductor substrate, wherein the contact is coupled to the bonding vias and the bonding wire layers.

17. The method of claim 16 , wherein the forming of the contact is performed before the forming of the TSV.

18. The method of claim 16 , wherein the contact has a higher thermal conductivity than the TSV.

19. The method of claim 16 , wherein the TSV has a topmost surface that is above a topmost surface of the contact when the first side of the semiconductor substrate is above a second side of the semiconductor substrate.

20. The method of claim 19 , wherein the topmost surface of the TSV is above the topmost surface of the contact by a first distance, and wherein the first distance is equal to a thickness of the second insulating layer.