Ferroelectric tunnel junction devices with discontinuous seed structure and methods for forming the same
A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.
1. A memory device comprising a memory cell comprising:
a bottom electrode layer;
a high-k dielectric layer disposed on the bottom electrode layer;
a discontinuous seed structure comprising particles of a metal disposed on the high-k dielectric layer;
a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and
a top electrode layer disposed on the FE layer.
2. The memory device of claim 1 , wherein the metal comprises W, Mo, or a combination thereof.
3. The memory device of claim 2 , wherein the seed structure has an average particle size ranging from about 1 angstrom to about 10 angstroms.
4. The memory device of claim 1 , wherein the high-k dielectric layer comprises AlO, MgO, LaAlO 3 , or a combination thereof.
5. The memory device of claim 4 , wherein the FE layer comprises HfO 2 , HfZrO, Pb[Zr x Ti 1-x ]O 3 , (0≤x≤1), PbTiO 3 , HfLaO, or a combination thereof.
6. The memory device of claim 4 , wherein a primary phase of the FE layer is an orthorhombic phase.
7. The memory device of claim 6 , wherein the orthorhombic phase represents from about 60 atomic percent (at %) to about 99.9 at % of the FE layer.
8. The memory device of claim 1 , further comprising:
a substrate;
a transistor disposed on the substrate, the transistor comprising:
a source region and a drain region formed in the substrate;
a channel region formed in the substrate between the source and drain regions;
a transistor high-k dielectric layer disposed on the channel region;
a gate electrode disposed on the transistor high-k dielectric layer;
wherein the bottom electrode layer of the memory cell is electrically connected to the source region or the drain region.
9. The memory device of claim 8 , further comprising:
a bit line electrically coupled to the source region;
a drain via contact electrically coupled to the drain region and the bottom electrode layer; and
a word line electrically coupled to the gate electrode.
10. A memory device comprising a memory cell comprising:
a high-k dielectric layer;
a discontinuous seed structure disposed on the high-k dielectric layer, the discontinuous seed structure comprising particles of a W, Mo, or a combination thereof; and
a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure.
11. The memory cell of claim 10 , wherein the seed structure has an average particle size ranging from about 1 angstrom to about 10 angstroms.
12. The memory cell of claim 10 , wherein the FE layer comprises HfO 2 , HfZrO, Pb[Zr x Ti 1-x ]O 3 , (0≤x≤1), PbTiO 3 , HfLaO, or a combination thereof.
13. The memory cell of claim 10 , wherein a primary phase of the FE layer is an orthorhombic phase.
14. The memory cell of claim 13 , wherein the orthorhombic phase represents from about 60 atomic percent (at %) to about 99.9 at % of the FE layer.
15. A method of forming a memory cell, comprising:
depositing a high-k dielectric layer over a substrate;
depositing a discontinuous seed structure comprising particles of a metal disposed on the high-k dielectric layer;
growing a ferroelectric (FE) layer on the seed structure and portions of the high-k dielectric layer exposed through the seed structure,
wherein the metal promotes the formation of an orthorhombic phase in the FE layer.
16. The method of claim 15 , further comprising:
depositing a bottom electrode layer on the substrate under the high-k dielectric layer; and
depositing a top electrode layer on the FE layer.
17. The method of claim 16 , wherein the depositing the seed structure comprises depositing from about ¼ to about ¾ of a mono-layer of metal atoms on the high-k dielectric layer.
18. The method of claim 16 , further comprising patterning the top electrode, the FE layer, the high-k dielectric layer, and the bottom electrode to form a memory cell.
19. The method of claim 18 , further comprising depositing an encapsulation layer on the memory cell.
20. The method of claim 19 , further comprising depositing dielectric layer on the encapsulation layer.