Semiconductor devices

1. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate;

a gate spacer on a sidewall of the gate structure; and

a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including:

a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and

a second portion extending from the first portion in a vertical direction substantially perpendicular to and away from an upper surface of the substrate; and

a capping layer on the polishing stop pattern,

wherein:

an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof,

the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof, and

an upper surface of the capping layer is substantially coplanar with the upper surface of the central portion of the first portion of the polishing stop pattern or the upper surface of the second portion of the polishing stop pattern.

2. The semiconductor device as claimed in claim 1 , wherein:

the substrate includes a first region and a second region,

the gate structure is a first gate structure on the first region of the substrate,

the gate spacer, the polishing stop pattern, and the capping layer are a first gate spacer, a first polishing stop pattern and a first capping layer, respectively,

the semiconductor device further comprises:

a second gate structure on the second region of the substrate;

a second gate spacer on a sidewall of the second gate structure;

a second polishing stop pattern on the second gate structure and the second gate spacer; and

a second capping layer on the second polishing stop pattern, the second polishing stop pattern including:

a first portion covering an upper surface of the second gate structure and an upper surface of the second gate spacer; and

a second portion extending from the first portion in the vertical direction, and

an upper surface of the second capping layer is substantially coplanar with an upper surface of the second portion of the second polishing stop pattern.

3. The semiconductor device as claimed in claim 1 , wherein an upper surface of a central portion of the gate structure contacting the central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the gate structure.

4. The semiconductor device as claimed in claim 3 , wherein:

the gate structure includes:

a second gate electrode;

a first gate electrode covering a sidewall and a lower surface of the second gate electrode;

a gate barrier covering a sidewall and a lower surface of the first gate electrode; and

a gate insulation pattern covering a sidewall and a lower surface of the gate barrier, and

an upper surface of the second gate electrode is higher than an uppermost surface of each of the first gate electrode, the gate barrier, and the gate insulation pattern.

5. The semiconductor device as claimed in claim 4 , wherein:

the second gate electrode includes tungsten,

the first gate electrode includes titanium aluminum carbide, and

the gate barrier includes titanium nitride.

6. The semiconductor device as claimed in claim 1 , wherein the polishing stop pattern includes silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or an amorphous carbon layer.

7. The semiconductor device as claimed in claim 1 , wherein the polishing stop pattern includes polysilicon or boronitride.

8. The semiconductor device as claimed in claim 1 , wherein the polishing stop pattern includes a transition metal.

9. The semiconductor device as claimed in claim 1 , further comprising:

a source/drain layer on a portion of the substrate adjacent to the gate structure;

a first insulating interlayer on the source/drain layer, the first insulating interlayer covering a sidewall of the gate spacer and a sidewall of the polishing stop pattern; and

a first contact plug extending through the first insulating interlayer to contact an upper surface of the source/drain layer,

wherein an upper surface of the first contact plug is substantially coplanar with the upper surface of the central portion of the first portion of the polishing stop pattern or the upper surface of the second portion of the polishing stop pattern.

10. The semiconductor device as claimed in claim 9 , further comprising an etch stop layer commonly on the polishing stop pattern, the first insulating interlayer, and the first contact plug.

11. The semiconductor device as claimed in claim 10 , further comprising:

a second contact plug extending through the etch stop layer to contact an upper surface of the first contact plug; and

a third contact plug extending through the etch stop layer and the polishing stop pattern to contact an upper surface of the gate structure.

12. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate;

a gate spacer on a sidewall of the gate structure; and

a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including:

a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and

a second portion extending from the first portion in a vertical direction substantially perpendicular to and away from an upper surface of the substrate,

wherein:

an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof,

the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof, and

an upper surface of a central portion of the gate structure contacting the central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the gate structure.