Semiconductor device and method

1. A method comprising:

forming a fin extending from a substrate;

forming an first isolation material along opposing sidewalls of the fin;

forming a dummy gate structure over the fin;

forming an epitaxial source/drain region in the fin adjacent the dummy gate structure;

forming an etch stop layer over the epitaxial source/drain region and over the dummy gate structure;

forming a protection layer over the etch stop layer, the protection layer comprising silicon oxynitride;

forming a second isolation material over the protection layer, wherein forming the second isolation material comprises performing an anneal process that reduces a nitrogen concentration of the protection layer, wherein the anneal process comprises controlling an anneal temperature or an anneal duration so that the nitrogen concentration in the protection layer is reduced by at least eighty-percent; and

after performing the anneal process, replacing the dummy gate structure with a replacement gate structure.

2. The method of claim 1 , wherein the second isolation material comprises silicon oxide.

3. The method of claim 1 , wherein forming the protection layer comprises using an atomic layer deposition (ALD) process.

4. The method of claim 1 , wherein, after forming the second isolation material, the protection layer has an atomic percentage of nitrogen that is less than 10%.

5. The method of claim 1 , wherein the anneal process converts the protection layer from silicon oxynitride to silicon oxide.

6. The method of claim 1 , wherein the protection layer has a thickness between 1 nm and 3 nm.

7. The method of claim 1 , wherein forming the second isolation material comprises a flowable chemical vapor deposition (FCVD) process.

8. The method of claim 1 , further comprising forming an opening extending through the second isolation material, the protection layer, and the etch stop layer to expose the epitaxial source/drain region, and depositing a conductive material within the opening.

9. A method of forming a semiconductor device, the method comprising:

forming a semiconductor fin protruding from a substrate;

forming a gate stack over the semiconductor fin;

forming a source/drain region on the semiconductor fin adjacent the gate stack;

forming a first dielectric layer extending over the source/drain region and over a topmost surface of the gate stack;

forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is a different material than the first dielectric layer, wherein the second dielectric layer is formed having a first atomic percentage of nitrogen, wherein the first dielectric layer and the second dielectric layer extend over the topmost surface of the gate stack after forming the second dielectric layer;

forming an insulating layer on the second dielectric layer, wherein the insulating layer is a different material than the second dielectric layer;

performing an annealing process, wherein the second dielectric layer has a second atomic percentage of nitrogen after performing the annealing process that is less than one-fifth of the first atomic percentage of nitrogen; and

after performing the annealing process, forming a conductive feature extending through the insulating layer, the second dielectric layer, and the first dielectric layer to contact the source/drain region.

10. The method of claim 9 , wherein the first dielectric layer is silicon nitride.

11. The method of claim 9 , wherein the first dielectric layer has a thickness between 2 nm and 100 nm.

12. The method of claim 9 , wherein the annealing process is performed at a temperature between 400° C. and 1000° C.

13. The method of claim 9 , wherein the second dielectric layer is silicon oxynitride, and wherein the first atomic percentage of nitrogen is between 1% and 20%.

14. The method of claim 9 , wherein the insulating layer is silicon oxide.

15. A method comprising:

forming a fin extending from a semiconductor substrate;

forming a dummy gate stack over and along a sidewall of the fin;

forming an epitaxial source/drain region in the fin adjacent the dummy gate stack;

depositing a silicon nitride layer on the epitaxial source/drain region;

depositing a silicon oxynitride layer on the silicon nitride layer;

depositing an insulating layer on the silicon oxynitride layer;

after depositing the insulating layer, converting an upper portion of the silicon oxynitride layer to a converted layer using an anneal process, wherein the converted layer comprises silicon and oxygen, and wherein the converted layer has a first atomic percentage of nitrogen that is less than one-fifth of a second atomic percentage of nitrogen of the silicon oxynitride layer;

after converting the upper portion of the silicon oxynitride layer to the converted layer, replacing the dummy gate stack with a replacement gate stack; and

forming a contact extending through the insulating layer, the converted layer, the silicon oxynitride layer, and the silicon nitride layer to the epitaxial source/drain region.

16. The method of claim 15 , wherein the insulating layer comprises silicon oxide.

17. The method of claim 15 , wherein the silicon oxynitride layer is thicker than the silicon nitride layer.

18. The method of claim 15 , wherein the silicon oxynitride layer has a thickness between 1 nm and 3 nm.

19. The method of claim 15 , wherein depositing the insulating layer comprises a flowable chemical vapor deposition (FCVD) process and a curing process, wherein the anneal process is the curing process.

20. The method of claim 15 , wherein the anneal process comprises:

reacting water with nitrogen atoms of the silicon oxynitride layer to produce NH 3 ; and

purging the NH 3 from a process chamber in which the anneal process is performed.