Semiconductor device and method

1. A device comprising:

a nanostructure;

a gate structure surrounding the nanostructure;

an epitaxial source/drain region adjacent the gate structure;

a dielectric feature adjacent the epitaxial source/drain region, a top surface of the dielectric feature being coplanar with a top surface of the gate structure;

a dielectric layer under the dielectric feature, the epitaxial source/drain region, and the gate structure; and

a power rail via extending through the dielectric layer and the dielectric feature, the power rail via physically and electrically coupled to a lower portion of the epitaxial source/drain region.

2. The device of claim 1 , wherein the power rail via comprises:

a first contact extending through the dielectric feature, the first contact physically separated from a sidewall of the epitaxial source/drain region; and

a second contact extending through the dielectric layer, the second contact physically and electrically coupled to the lower portion of the epitaxial source/drain region.

3. The device of claim 1 further comprising:

a conductive line on the dielectric layer and the power rail via.

4. The device of claim 1 , wherein the power rail via extends into the lower portion of the epitaxial source/drain region.

5. The device of claim 1 further comprising:

a spacer between the epitaxial source/drain region and the power rail via.

6. The device of claim 1 further comprising:

a first interlayer dielectric on the epitaxial source/drain region;

a source/drain contact extending through the first interlayer dielectric, the source/drain contact physically and electrically coupled to an upper portion of the epitaxial source/drain region;

a second interlayer dielectric on the source/drain contact and the first interlayer dielectric; and

a shared contact in the second interlayer dielectric, the shared contact physically and electrically coupled to the source/drain contact and the power rail via.

7. The device of claim 6 further comprising:

a dielectric plug in the second interlayer dielectric, the dielectric plug covering the shared contact.

8. A device comprising:

a first interconnect structure comprising a first conductive line;

a second interconnect structure comprising a second conductive line;

a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising a spacer and a first transistor, the first transistor comprising an epitaxial source/drain region; and

a conductive via extending through the device layer, the conductive via connecting the first conductive line to the second conductive line, the conductive via contacting a bottom surface of the epitaxial source/drain region, the spacer separating the conductive via from a sidewall of the epitaxial source/drain region.

9. The device of claim 8 , wherein a width of the second conductive line is greater than a width of the first conductive line.

10. The device of claim 8 , wherein the first conductive line is an interconnect and the second conductive line is a power rail.

11. The device of claim 8 , wherein the device layer further comprises:

a first dielectric layer above the epitaxial source/drain region; and

a second dielectric layer under the epitaxial source/drain region, the conductive via extending through the first dielectric layer and the second dielectric layer.

12. The device of claim 11 , wherein the conductive via comprises:

a first contact extending through the first dielectric layer; and

a second contact extending through the second dielectric layer.

13. A method comprising:

forming a nanostructure above a fin;

forming a first gate structure around the nanostructure;

growing an epitaxial source/drain region adjacent to the first gate structure;

depositing a first dielectric layer on the epitaxial source/drain region;

replacing the first gate structure with dielectric feature;

forming a first contact and a second contact, the first contact extending through the first dielectric layer to contact the epitaxial source/drain region, the second contact extending through the dielectric feature, the second contact physically separated from a sidewall of the epitaxial source/drain region; and

forming a third contact through the fin to contact the epitaxial source/drain region and the second contact.

14. The method of claim 13 further comprising:

forming a second gate structure around the nanostructure, the epitaxial source/drain region disposed between the dielectric feature and the second gate structure.

15. The method of claim 13 further comprising:

forming a spacer separating the epitaxial source/drain region from the second contact.

16. The method of claim 13 further comprising:

forming a power rail contacting the third contact.

17. The method of claim 13 further comprising:

depositing a second dielectric layer on the first dielectric layer; and

forming a shared contact in the second dielectric layer, the shared contact contacting the first contact and the second contact.

18. The method of claim 17 further comprising:

forming a dielectric plug in the second dielectric layer, the dielectric plug disposed on the shared contact.

19. The method of claim 18 further comprising:

forming an interconnect structure on the second dielectric layer and the dielectric plug.

20. The method of claim 13 , wherein forming the second contact comprises:

etching an opening through the dielectric feature by etching the dielectric feature with a dry etch using a fluorine-based gas; and

forming a conductive material in the opening.