Counter for preventing completion of a thread including a non-blocking external device call with no-return indication
Devices and techniques for non-blocking external device calls are described herein. Specifically, when a processor receives an instruction with a no-return indication from a thread for a device, the processor can increase a counter corresponding to the thread based on the no-return indication. The processor can then continue execution of the thread without waiting for a return value from the device. When a return value is received for the instruction, the processor can decrement the counter. While the counter is not zero, the processor prevents the thread from completing (exiting).
1. A system comprising:
a first memory-compute node including a device configured to accept a remote call; and
a second memory-compute node including:
a hybrid-threading processor (HTP) including processing circuitry configured to:
receive an instruction from a thread for the device, the instruction corresponding to a no-return indication;
increase a counter corresponding to the thread based on the no-return indication;
continue execution of the thread irrespective of a return value from the device;
decrement the counter based on receipt of the return value; and
prevent the thread from completing until the counter is zero by removing a thread return instruction from execution when the counter is greater than zero.
2. The system of claim 1 , wherein, to continue execution of the thread, the processing circuitry is configured to place an identifier of the thread into a ready-to-run queue of the HTP.
3. The system of claim 1 , wherein the processing circuitry is further configured to:
receive the return value; and
discard the return value.
4. The system of claim 1 , wherein the device is a memory controller.
5. The system of claim 4 , wherein the instruction corresponding to the no-return indication is an atomic operation.
6. The system of claim 5 , wherein the return value is a result of the atomic operation.
7. The system of claim 5 , wherein the return value indicates whether the atomic operation completed successfully without including a result of the atomic operation.
8. The system of claim 5 , wherein the atomic operation is a programmable atomic operation.
9. The system of claim 1 , wherein the first memory-compute node is the second memory-compute node.
10. The system of claim 1 , wherein the counter is a sole counter used for every no-return instruction of the thread to a device outside of the HTP.
11. The system of claim 1 , wherein the no-return indication is included in the instruction.
12. The system of claim 11 , wherein the no-return indication is a single bit.
13. The system of claim 12 , wherein the single bit is one of several in an operation code field of the instruction corresponding to the no-return indication.
14. An apparatus comprising:
an interface to a device; and
processing circuitry configured to:
receive an instruction from a thread for the device, the instruction corresponding to a no-return indication;
make a call to the device across the interface in response to receipt of the instruction;
increase a counter corresponding to the thread based on the no-return indication;
continue execution of the thread without waiting for a return value from the device;
decrement the counter based on receipt of the return value; and
prevent the thread from completing until the counter is zero by removing a thread return instruction from execution when the counter is greater than zero.
15. The apparatus of claim 14 , wherein, to continue execution of the thread, the processing circuitry is configured to place an identifier of the thread into a ready-to-run queue of the apparatus.
16. The apparatus of claim 14 , wherein the device is a memory controller.
17. The apparatus of claim 16 , wherein the instruction corresponding to the no-return indication is an atomic operation.
18. The apparatus of claim 17 , wherein the return value is a result of the atomic operation.
19. The apparatus of claim 17 , wherein the return value indicates whether the atomic operation completed successfully without including a result of the atomic operation.
20. The apparatus of claim 17 , wherein the atomic operation is a programmable atomic operation.
21. The apparatus of claim 14 , wherein the apparatus is a hybrid threading processor.
22. The apparatus of claim 14 , wherein the counter is a sole counter used for every no-return instruction of the thread to a device outside of the apparatus.
23. The apparatus of claim 14 , wherein the no-return indication is included in the instruction corresponding to the no-return indication.
24. The apparatus of claim 14 , wherein the processing circuitry is further configured to:
receive the return value; and
discard the return value.