Memory controller based on flush operation and method of operating the same
The present technology includes a memory controller that allocates a new buffer memory area in a buffer memory or stores temporarily stored data in the buffer memory into a memory device based on a state of an auxiliary power device that supplies power to the memory device and the memory controller, and a power state of a host.
1. A memory controller that controls an operation of a memory device including a plurality of memory areas, the memory controller comprising:
a buffer memory configured to store data in an allocated buffer area among a plurality of buffer areas; and
a buffer memory controller configured to control the buffer memory and the memory device to store the data stored in the allocated buffer area and dummy data into the memory device, based on information on power to be provided from a host to the memory controller when supply of main power provided to the memory controller is cut off.
2. The memory controller of claim 1 , wherein the buffer memory controller comprises:
a state storage configured to store buffer state information on a state of the allocated buffer area; and
a flush controller configured to control the buffer memory and the memory device to store the data stored in the allocated buffer area and the dummy data into the memory device, based on the buffer state information, in response to the information that an amount of the power is less than a threshold value.
3. The memory controller of claim 1 , wherein the buffer memory controller allocates a new buffer area among the plurality of buffer areas in response to the information that an amount of the power is equal to or greater than a threshold value.
4. The memory controller of claim 2 , wherein the threshold value is determined according to an amount of power required to store the data.
5. The memory controller of claim 2 , wherein the buffer state information includes information on a size of the data stored in the allocated buffer area.
6. The memory controller of claim 5 , wherein the allocated buffer area is a buffer area which stores the data having a largest size from among data stored in each of the plurality of buffer areas.
7. A memory controller that controls an operation of a memory device including a plurality of memory areas, the memory controller comprising:
a buffer memory configured to store data in an allocated buffer area among a plurality of buffer areas; and
a buffer memory controller configured to:
control the buffer memory and the memory device to store the data stored in the allocated buffer area into the memory device, based on power information on power to be provided from a host to the memory controller when supply of main power provided to the memory controller is cut off, and
request new power information from the host after the data is stored in the memory device.
8. The memory controller of claim 7 , wherein the buffer memory controller comprises:
a state storage configured to store buffer state information on a state of the allocated buffer area; and
a flush controller configured to control the buffer memory and the memory device to store the data stored in the allocated buffer area into the memory device, based on the buffer state information, in response to the power information or the new power information that an amount of the power is less than a threshold value.
9. The memory controller of claim 7 , wherein the buffer memory controller allocates a new buffer area among the plurality of buffer areas in response to the power information or the new power information that an amount of the power is equal to or greater than a threshold value.
10. The memory controller of claim 8 , wherein the threshold value is determined according to an amount of power required to store the data.
11. The memory controller of claim 8 , wherein the buffer state information includes information on a size of the data stored in the allocated buffer area.
12. The memory controller of claim 11 , wherein the allocated buffer area is a buffer area which stores the data having a largest size from among data stored in each of the plurality of buffer areas.
13. A memory controller that controls an operation of a memory device including a plurality of memory areas, the memory controller comprising:
a buffer memory configured to store data in an allocated buffer area among a plurality of buffer areas; and
a buffer memory controller configured to:
provide to the host a delay response for delaying allocation of a new buffer area, based on buffer state information on a state of allocated buffer areas among the plurality of buffer areas, and
control the buffer memory and the memory device to store the data stored in the allocated buffer area into the memory device, based on information on power to be provided from a host to the memory controller when supply of main power provided to the memory controller is cut off.
14. The memory controller of claim 13 , wherein the buffer memory controller comprises a state storage configured to store the buffer state information, and
wherein the buffer memory controller provides to the host the delay response, when the buffer state information indicates that a number of the allocated buffer areas is less than a reference value.
15. The memory controller of claim 14 , wherein the buffer memory controller comprises:
a flush controller configured to control the buffer memory and the memory device to store the data stored in the allocated buffer area into the memory device, in response to the information that an amount of the power is less than a threshold value.
16. The memory controller of claim 14 , wherein the buffer memory controller allocates the new buffer area among the plurality of buffer areas, when the buffer state information indicates that the number of the allocated buffer areas is equal to or greater than the reference value, and the information indicates that an amount of the power is equal to or greater than a threshold value.
17. The memory controller of claim 13 , wherein the buffer state information includes information on a size of data stored in each of the allocated buffer areas, and
wherein the allocated buffer area is a buffer area which stores the data having a largest size from among the data stored in each of the allocated buffer areas.