Net-based wafer inspection
A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.
1. A method, comprising:
creating a defect map by merging defects from multiple dies that each includes a copy of an integrated circuit (IC);
determining layout shapes that overlap with the defects in the defect map;
determining connectivity between the layout shapes; and
grouping the defects into defect groups based on the connectivity between the layout shapes, wherein each defect group comprises defects that overlap with layout shapes that are electrically connected to each other.
2. The method of claim 1 , wherein the determining the connectivity between the layout shapes comprises tracing electrical connectivity between the layout shapes across one or more layers of the IC.
3. The method of claim 1 , comprising selecting defect groups that include more than a threshold number of defects.
4. The method of claim 1 , comprising selecting defect groups based on attributes of the defects.
5. The method of claim 4 , wherein the selecting the defect groups based on the attributes of the defects comprises selecting defect groups having at least one defect with a size greater than a threshold size.
6. The method of claim 1 , comprising selecting defect groups based on the associated layout data, netlist data, or both layout data and netlist data.
7. The method of claim 6 , wherein the selecting the defect groups based on the associated layout data, netlist data, or both layout data and netlist data comprises selecting defect groups associated with critical nets.
8. The method of claim 6 , wherein the selecting the defect groups based on the associated layout data, netlist data, or both layout data and netlist data comprises selecting defect groups associated with nets having a width less than a threshold width.
9. A system, comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
create a defect map by merging defects from multiple dies that include copies of an integrated circuit (IC);
determine layout shapes that overlap with the defects in the defect map;
determine connectivity between the layout shapes; and
group the defects into defect groups based on the connectivity between the layout shapes, wherein each defect group comprises defects that overlap with layout shapes that are electrically connected to each other.
10. The system of claim 9 , wherein the instructions when executed cause the processor to select defect groups based on a count of defects in the defect groups.
11. The system of claim 10 , wherein the selecting the defect groups based on the count of defects in the defect groups comprises selecting the defect groups that include more than a threshold number of defects.
12. The system of claim 9 , wherein the instructions when executed cause the processor to select defect groups based on attributes of the defects.
13. The system of claim 12 , wherein the selecting the defect groups based on the attributes of the defects comprises selecting defect groups having at least one defect with a size greater than a threshold size.
14. The system of claim 9 , wherein the instructions when executed cause the processor to select defect groups based on the associated layout data, netlist data, or both layout data and netlist data.
15. The system of claim 14 , wherein the selecting the defect groups based on the associated layout data, netlist data, or both layout data and netlist data comprises selecting defect groups associated with critical nets.
16. The system of claim 14 , wherein the selecting the defect groups based on the associated layout data, netlist data, or both layout data and netlist data comprises selecting defect groups associated with nets having a width less than a threshold width.
17. A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
create a database that enables layout data, netlist data, or both layout data and netlist data of an integrated circuit (IC) design to be looked up based on a location of a defect in a die that includes the IC;
create a defect map by merging defects from multiple dies that include copies of the IC;
for each defect in the defect map, look up layout data, netlist data, or both layout data and netlist data based on the location of the defect using the database; and
group the defects into defect groups based on the associated layout data, netlist data, or both layout data and netlist data.
18. The non-transitory computer-readable medium of claim 17 , wherein the instructions when executed cause the processor to assign priorities to the defect groups based on a count of defects in the defect groups, and perform repeater insertion on the defect groups in order of the assigned priorities.
19. The non-transitory computer-readable medium of claim 17 , wherein the instructions when executed cause the processor to assign priorities to the defect groups based on attributes of the defects, and perform repeater insertion on the defect groups in order of the assigned priorities.
20. The non-transitory computer-readable medium of claim 17 , wherein the instructions when executed cause the processor to assign priorities to the defect groups based on the associated layout data, netlist data, or both layout data and netlist data, and perform repeater insertion on the defect groups in order of the assigned priorities.