Automatic generation of layouts for analog integrated circuits

1. A method, comprising:

receiving, by a processing device, device specifications for an analog integrated circuit;

generating, by the processing device, a non-final layout of the analog integrated circuit using the device specifications;

partitioning, by the processing device, the non-final layout into a plurality of sub-cells;

performing, by the processing device, a quality control check on each sub-cell in the plurality of sub-cells to produce verified sub-cells;

merging, by the processing device, the verified sub-cells to form a merged layout of the analog integrated circuit; and

performing, by the processing device, a quality control check on the merged layout to produce a verified merged layout,

wherein partitioning the non-final layout into the plurality of sub-cells comprises:

receiving, by the processing device, partition information on the non-final layout;

determining, by the processing device, based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction in the non-final layout of the analog integrated circuit;

determining, by the processing device, based on the device specifications and the partition information, second cut locations for a second set of cuts to be made along a second direction in the non-final layout of the analog integrated circuit;

causing, by the processing device, the non-final layout of the analog integrated circuit to be cut at the first cut locations to define a temporary layout; and

causing, by the processing device, the temporary layout to be cut at the second cut locations to define the plurality of sub-cells.

2. The method of claim 1 , further comprising providing the verified merged layout to a process design kit.

3. The method of claim 2 , wherein providing the verified merged layout to the process design kit comprises including each verified sub-cell in a library.

4. The method of claim 1 , wherein the partition information comprises, for each sub-cell, a cell type, a starting point and an ending point along the first direction, and a starting point and an ending point along the second direction.

5. The method of claim 1 , wherein performing the quality control check on each sub-cell in the plurality of sub-cells comprises performing design rule checking on each sub-cell in the plurality of sub-cells.

6. The method of claim 1 , wherein performing the quality control check on each sub-cell in the plurality of sub-cells comprises performing layout versus layout verification on each sub-cell in the plurality of sub-cells.

7. The method of claim 1 , wherein performing the quality control check on the merged layout comprises performing layout versus layout verification on the merged layout.

8. The method of claim 1 , wherein the partition information includes cell types of sub-cells in the plurality of sub-cells, orientations of the sub-cells in the plurality of sub-cells, a minimum number of rows of the sub-cells in the plurality of sub-cells, and an arrangement of the sub-cells in the plurality of sub-cells.

9. A system, comprising:

a processing device; and

a storage device operably connected to the processing device and storing instructions, that when executed by the processing device, cause operations to be performed, the operations comprising:

receiving device specifications for an analog integrated circuit;

generating a non-final layout of the analog integrated circuit using the device specifications;

partitioning the non-final layout into a plurality of sub-cells;

performing a quality control check on each sub-cell in the plurality of sub-cells to produce verified sub-cells;

merging the verified sub-cells to form a merged layout of the analog integrated circuit; and

performing a quality control check on the merged layout to produce a verified merged layout,

wherein partitioning the non-final layout into the plurality of sub-cells includes receiving, by the processing device, partition information on the non-final layout, the partition information including, for each sub-cell, a cell type, a starting point and an ending point along a first direction, and a starting point and an ending point along a second direction for partitioning the non-final layout into the plurality of sub-cells.

10. The system of claim 9 , wherein:

the system further comprises a display; and

the storage device stores further instructions for generating a user interface and causing the user interface to be displayed on the display.

11. The system of claim 10 , wherein the user interface comprises:

a cell placement view;

a device mapping view;

a column entry field;

a row entry field;

a column spacing entry field;

a row spacing entry field; and

a base pattern entry field.

12. The system of claim 9 , wherein the storage device stores further instructions for providing the verified merged layout to a process design kit.

13. The system of claim 9 , wherein partitioning the non-final layout into the plurality of sub-cells comprises:

determining, by the processing device, based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along the first direction in the non-final layout of the analog integrated circuit;

based on the device specifications and the partition information, determining, by the processing device, second cut locations for a second set of cuts to be made along a second direction in the non-final layout of the analog integrated circuit;

causing, by the processing device, the non-final layout of the analog integrated circuit to be cut at the first cut locations to produce a temporary layout; and

causing, by the processing device, the temporary layout to be cut at the second cut locations to produce the plurality of sub-cells.

14. The system of claim 9 , wherein performing the quality control check on each sub-cell in the plurality of sub-cells comprises performing design rule checking on each sub-cell in the plurality of sub-cells.

15. The system of claim 9 , wherein performing the quality control check on each sub-cell in the plurality of sub-cells comprises performing layout versus layout verification on each sub-cell in the plurality of sub-cells.

16. The system of claim 9 , wherein performing the quality control check on the merged layout comprises performing layout versus layout verification on the merged layout.

17. The method of claim 9 , wherein the partition information includes orientations of sub-cells in the plurality of sub-cells, a minimum number of rows of the sub-cells in the plurality of sub-cells, and an arrangement of the sub-cells in the plurality of sub-cells.

18. A method, comprising:

receiving, by a processing device, device specifications for an analog integrated circuit;

generating, by the processing device, a non-final layout of the analog integrated circuit using the device specifications;

partitioning, by the processing device, the non-final layout into a plurality of sub-cells;

performing, by the processing device, a quality control check on each sub-cell in the plurality of sub-cells to produce verified sub-cells;

merging, by the processing device, the verified sub-cells to form a merged layout of the analog integrated circuit;

performing, by the processing device, a quality control check on the merged layout to produce a verified merged layout; and

providing the verified merged layout to a process design kit, wherein partitioning the non-final layout into the plurality of sub-cells comprises:

receiving, by the processing device, partition information on the non-final layout;

based on the device specifications and the partition information, determining, by the processing device, first cut locations for a first set of cuts to be made along a first direction in the non-final layout of the analog integrated circuit;

based on the device specifications and the partition information, determining, by the processing device, second cut locations for a second set of cuts to be made along a second direction in the non-final layout of the analog integrated circuit;

causing, by the processing device, the non-final layout of the analog integrated circuit to be cut at the first cut locations to define a temporary layout; and

causing, by the processing device, the temporary layout to be cut at the second cut locations to define the plurality of sub-cells.

19. The method of claim 18 , wherein the partition information comprises, for each sub-cell, a cell type, a starting point and an ending point along the first direction, and a starting point and an ending point along the second direction.

20. The method of claim 18 , wherein performing the quality control check on each sub-cell in the plurality of sub-cells comprises performing layout versus layout verification on each sub-cell in the plurality of sub-cells.