Disaggregation of system-on-chip (SOC) architecture
Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
1. An apparatus comprising:
a package assembly comprising a plurality of distinct chiplets and a plurality of interconnect structures, the plurality of distinct chiplets including:
a first chiplet comprising a first base chiplet coupled to a bridge interconnect and an interconnect structure, the first base chiplet including:
an interconnect fabric, and
a first plurality of Level 3 (L3) cache banks to cache data read from and transmitted to a memory;
a second chiplet comprising a second base chiplet, the second chiplet coupled to the first chiplet over the bridge interconnect; and
a third chiplet including a second plurality of L3 cache banks, the third chiplet stacked on the first base chiplet in a three-dimensional (3D) arrangement and coupled to the first base chiplet over the interconnect structure.
2. The apparatus of claim 1 , wherein the second plurality of L3 cache banks are SRAM cache banks.
3. The apparatus of claim 1 , wherein the first chiplet further comprises:
one or more execution units to execute instructions, the one or more execution units coupled to the second chiplet over the bridge interconnect.
4. The apparatus of claim 1 , wherein the second chiplet comprises an input/output, I/O, chiplet to couple to one or more additional chiplets.
5. The apparatus of claim 4 , wherein the second chiplet is to be coupled to the third chiplet over the bridge interconnect.
6. The apparatus of claim 1 , wherein one or more of the plurality of distinct chiplets further comprise:
power control logic to configure dynamic voltage and frequency scaling for chiplets in the plurality of distinct chiplets.
7. The apparatus of claim 6 , wherein each chiplet in the plurality of distinct chiplets has an independent clock domain and an independent power domain.
8. The apparatus of claim 1 , wherein at least one of the plurality of distinct chiplets comprises a plurality of processing cores.
9. The apparatus of claim 1 , wherein the third chiplet is bonded to the first base chiplet.
10. The apparatus of claim 1 , wherein the third chiplet is a memory chiplet.
11. A system comprising:
a memory chiplet; and
a processor including a package assembly comprising a plurality of distinct chiplets and a plurality of interconnect structures, the plurality of distinct chiplets including:
a first chiplet comprising a first base chiplet coupled to a bridge interconnect and an interconnect structure, the first base chiplet including:
an interconnect fabric, and
a first plurality of Level 3 (L3) cache banks to cache data read from and transmitted to a memory;
a second chiplet comprising a second base chiplet, the second chiplet coupled to the first chiplet over the bridge interconnect; and
a third chiplet including a second plurality of L3 cache banks, the third chiplet stacked on the first base chiplet in a three-dimensional (3D) arrangement and coupled to the first base chiplet over the interconnect structure.
12. The system of claim 11 , wherein the second plurality of L3 cache banks are SRAM cache banks.
13. The system of claim 11 , wherein the first chiplet further comprises:
one or more execution units to execute instructions, the one or more execution units coupled to the second chiplet over the bridge interconnect.
14. The system of claim 11 , wherein the second chiplet comprises an input/output, I/O, chiplet to couple to one or more additional chiplets.
15. The system of claim 14 , wherein the second chiplet is to be coupled to the third chiplet over the bridge interconnect.
16. The system of claim 11 , wherein one or more of the plurality of distinct chiplets further comprise:
power control logic to configure dynamic voltage and frequency scaling for chiplets in the plurality of distinct chiplets.
17. The system of claim 16 , wherein each chiplet in the plurality of distinct chiplets has an independent clock domain and an independent power domain.
18. The system of claim 11 , wherein at least one of the plurality of distinct chiplets comprises a plurality of processing cores.
19. The system of claim 11 , wherein the third chiplet is bonded to the first base chiplet.
20. The system of claim 11 , wherein the third chiplet is a memory chiplet.