Apparatuses, systems, and methods for ferroelectric memory cell operations
Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced signal on a coupled digit line. To improve the performance while maintaining increased speed, two digit lines may be coupled to the same sense amplifier, so that the FeRAM cells coupled to both digit lines contribute signal to the sense amplifier. For example a first digit line in a first deck of the memory and a second digit line in a second deck of the memory may both be coupled to the sense amplifier. In some embodiments, additional digit lines may be used as shields (e.g., by coupling the shield digit lines to a ground voltage) to further improve the signal-to-noise ratio.
1. An apparatus, comprising:
a first memory cell region comprising a first plurality of ferroelectric memory (FeRAM) cells operated across a first charge range of the first plurality of FeRAM cells; and
a second memory cell region comprising a second plurality of FeRAM cells operated across a second charge range of the second plurality of FeRAM cells, wherein
as part of a write operation, the same information is written to more than one of the first plurality of FeRAM cells of the first memory cell region.
2. The apparatus of claim 1 , wherein the first charge range is smaller than the second charge range.
3. An apparatus, comprising:
a first memory cell region comprising a first plurality of ferroelectric memory (FeRAM) cells operated across a first charge range of the first plurality of FeRAM cells; and
a second memory cell region comprising a second plurality of FeRAM cells operated across a second charge range of the second plurality of FeRAM cells, wherein
the first memory cell region comprises a plurality of first digit lines each coupled to one of the first plurality of FeRAM cells and a plurality of second digit lines coupled to a ground voltage.
4. The apparatus of claim 3 , wherein each of the plurality of first digit lines coupled to the one of the first plurality of FeRAM cells is adjacent to one or more of the plurality of second digit lines coupled to the ground voltage.
5. An apparatus, comprising:
a first memory cell region comprising a first plurality of ferroelectric memory (FeRAM) cells operated across a first charge range of the first plurality of FeRAM cells; and
a second memory cell region comprising a second plurality of FeRAM cells operated across a second charge range of the second plurality of FeRAM cells, wherein
the second plurality of FeRAM cells each include a leaker layer and the first plurality of FeRAM cells do not include a leaker layer.
6. An apparatus, comprising:
a first memory cell region comprising a first plurality of ferroelectric memory (FeRAM) cells operated across a first charge range of the first plurality of FeRAM cells
a second memory cell region comprising a second plurality of FeRAM cells operated across a second charge range of the second plurality of FeRAM cells;
a first plurality of sense amplifiers each coupled to more than one FeRAM cell of the first plurality of FeRAM cells; and
a second plurality of sense amplifiers each coupled to one FeRAM cell of the second plurality of FeRAM cells.
7. A method, comprising:
operating a first memory cell region including a first plurality of ferroelectric memory (FeRAM) cells across a first charge range of the first plurality of FeRAM cells:
operating a second memory cell region including a second plurality of FeRAM cells across a second charge range of the second plurality of FeRAM cells, further comprising; and
writing a bit of information to multiple of the first plurality of memory cells as part of a write operation.
8. The method of claim 7 , further comprising writing the bit of information to a first one of the first plurality of memory cells in a first deck and to a second one of the first plurality of memory cells in a second deck.
9. The method of claim 7 , further comprising writing a different bit to each of the second plurality of memory cells.
10. A method, comprising:
operating a first memory cell region including a first plurality of ferroelectric memory (FeRAM) cells across a first charge range of the first plurality of FeRAM cells;
operating a second memory cell region including a second plurality of FeRAM cells across a second charge range of the second plurality of FeRAM cells; and
storing information in alternating ones of the first plurality of memory cells, wherein
ones of the first plurality of memory cells between the alternating ones of the first plurality of memory cells are coupled to a ground voltage.
11. A method, comprising:
operating a first memory cell region including a first plurality of ferroelectric memory (FeRAM) cells across a first charge range of the first plurality of FeRAM cells;
operating a second memory cell region including a second plurality of FeRAM cells across a second charge range of the second plurality of FeRAM cells;
operating the first memory cell region across a dielectric region of the first plurality of FeRAM cells; and
operating the second memory cell region across a full-range region of the second plurality of FeRAM cells.
12. A method, comprising:
operating a first memory cell region including a first plurality of ferroelectric memory (FeRAM) cells across a first charge range of the first plurality of FeRAM cells;
operating a second memory cell region including a second plurality of FeRAM cells across a second charge range of the second plurality of FeRAM cells;
accessing the first plurality of FeRAM cells with a first speed; and
accessing the second plurality of FeRAM cells with a second speed which is slower than the first speed.