IP Library › Granted Patent US 11,764,179
Granted Patent B2
US 11,764,179 · App. 16/994,483 · Granted Sep 19, 2023

Semiconductor device package

Inventor: Zhi-Yuan Lin (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L24/14H01L21/56H01L21/563H01L21/76877H01L23/31H01L23/498H01L23/49816
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,764,179
App. No.
16/994,483
Granted
Sep 19, 2023
Kind
B2
Abstract

The present disclosure provides a semiconductor device package. The semiconductor device package includes a conductive pillar having a first surface, a second surface, and a lateral surface extending between the first surface and the second surface. The lateral surface has a first part and a second part connected to the first part. The semiconductor device package also includes a barrier layer in contact with the first part of the lateral surface of the conductive pillar and an encapsulant in contact with the second part of the lateral surface of the conductive pillar. The semiconductor device package also includes a first flowable conductive material disposed on the first surface of the conductive pillar. A method of manufacturing a semiconductor device package is also disclosed.

Claims (18)

1. A semiconductor device package, comprising:

a substrate; and

a structure including:

a barrier layer;

a first conductive pillar having a first portion disposed within the barrier layer and a second portion disposed between a bottom surface of the barrier layer and the substrate;

an encapsulant encapsulating the second portion of the first conductive pillar;

an oxidation layer disposed over a first part of a lateral surface of the second portion of the first conductive pillar, wherein a second part of the lateral surface of the first conductive pillar is exposed from the oxidation layer;

a flowable conductive material in contact with the second part of the lateral surface of the second portion of the first conductive pillar, wherein a first portion of the flowable conductive material is disposed between the first conductive pillar and the oxidation layer,

wherein the first portion of the first conductive pillar and the second portion of the first conductive pillar are connected at an interface between the barrier layer and the encapsulant, and a width of the first portion of the first conductive pillar and a width of the second portion of the first conductive pillar are substantially the same from a cross-sectional view.

2. The semiconductor device package of claim 1 , further comprising:

a second conductive pillar adjacent to the first conductive pillar and having a third portion disposed within the barrier layer and a fourth portion disposed between the bottom surface of the barrier layer and the substrate,

wherein a top surface of the first portion of the first conductive pillar and a top surface of the third portion of the second conductive pillar are exposed from the barrier layer, and wherein a distance between the top surface of the first portion of the first conductive pillar and the top surface of the third portion of the second conductive pillar is substantially the same as a distance between the second portion of the first conductive pillar and the fourth portion of the second conductive pillar.

3. The semiconductor device package of claim 1 , wherein a length of the first part of the lateral surface of the second portion of the first conductive pillar is greater than a length of the second part of the lateral surface of the second portion of the first conductive pillar.

4. The semiconductor device package of claim 1 , wherein a second portion of the flowable conductive material covers a lateral surface of the oxidation layer.

5. The semiconductor device package of claim 1 , wherein the oxidation layer extends from the bottom surface of the barrier layer toward a bottom surface of the second portion of the first conductive pillar.

6. The semiconductor device package of claim 1 , further comprising:

an electronic component disposed over the substrate; and

the encapsulant disposed over the substrate and covering the electronic component, wherein a part of the encapsulant is disposed between the substrate and the electronic component.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2020
From: LIN, ZHI-YUAN
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 054133/0325 →
Continuity (1)
Related Publication 20220052004A1 · Feb 17, 2022
Cited By (2)
US 12,580,126 US 12,614,677