Amphi-FET structure, method of making and method of designing
A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.
1. A semiconductor device comprising:
a substrate;
a first active region on a first side of the substrate;
a first gate structure surrounding a first portion of the first active region;
a second active region on a second side of the substrate, wherein the second side is opposite the first side;
a second gate structure surrounding a first portion of the second active region; and
a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.
2. The semiconductor device of claim 1 , wherein the gate via has a tapered profile.
3. The semiconductor device of claim 1 , wherein the gate via has a uniform width.
4. The semiconductor device of claim 1 , further comprising:
a conductive line, wherein the first gate structure is between the conductive line and the substrate; and
a first via, wherein the first via electrically connects the conductive line to the first gate structure.
5. The semiconductor device of claim 4 , wherein the first via is aligned with the gate via.
6. The semiconductor device of claim 4 , wherein a size of the first via is equal to a size of the gate via.
7. The semiconductor device of claim 1 , further comprising:
a first source/drain (S/D) electrode surrounding a second portion of the first active region;
a second S/D electrode surrounding a second portion of the second active region; and
a S/D connect via extending through the substrate, wherein the S/D connect via directly connects to the first S/D electrode, and the S/D connect via directly connects to the second S/D electrode.
8. The semiconductor device of claim 7 , wherein a width of the S/D connect via parallel to the first side of the substrate is equal to a width of the first S/D electrode.
9. The semiconductor device of claim 7 , wherein the S/D connect via has a tapered profile.
10. The semiconductor device of claim 7 , wherein the S/D connect via has a uniform width.
11. The semiconductor device of claim 7 , further comprising:
a third S/D electrode surrounding a third portion of the first active region; and
a fourth S/D electrode surrounding a third portion of the second active region, wherein a region of the substrate between the third S/D electrode and the fourth S/D electrode is free of a conductive element.
12. The semiconductor device of claim 1 , further comprising:
a third gate structure surrounding a second portion of the first active region; and
a fourth gate structure surrounding a second portion of the second active region; and
a second gate via extending through the substrate, wherein the second gate via directly connects to the third gate structure, and the second gate via directly connects to the fourth gate structure.
13. The semiconductor device of claim 1 , wherein the first active region comprises at least one nanosheet.
14. A semiconductor device comprising:
a substrate;
a first active region on a first side of the substrate;
a first gate structure in contact with the first active region;
a second active region on a second side of the substrate, wherein the second side is opposite the first side;
a second gate structure in contact with the second active region; and
a gate via extending through the substrate, wherein the gate via electrically connects to the first gate structure, and the gate via electrically connects to the second gate structure.
15. The semiconductor device of claim 14 , wherein the gate via is offset from the first active region in a direction parallel to a surface of the substrate closest to the first active region.
16. The semiconductor device of claim 14 , wherein the first gate structure is between the substrate and the first active region.
17. The semiconductor device of claim 14 , wherein the second gate structure is between the substrate and the second active region.
18. A semiconductor device comprising:
a substrate;
a first active region on a first side of the substrate;
a first contact structure surrounding a first portion of the first active region;
a second active region on a second side of the substrate, wherein the second side is opposite the first side;
a second contact structure surrounding a first portion of the second active region; and
a contact via extending through the substrate, wherein the contact via directly connects to the first contact structure, and the gate via directly connects to the second contact structure.
19. The semiconductor device of claim 18 , further comprising:
a first gate structure surrounding a first portion of the first active region; and
a second gate structure surrounding a first portion of the second active region.
20. The semiconductor device of claim 19 , further comprising a gate via extending through the substrate, wherein the gate via electrically connects the first gate structure to the second gate structure.