FinFETs having step sided contact plugs and methods of manufacturing the same

1. A semiconductor device comprising:

a substrate;

an isolation layer on the substrate;

a plurality of active fins protruding from the substrate and extending through the isolation layer in a vertical direction;

a gate structure on the plurality of active fins and the isolation layer;

a source/drain on the plurality of active fins and the isolation layer;

a contact plug on and contacting the source/drain; and

an interlayer insulating structure on the isolation layer,

wherein the gate structure includes a gate dielectric and a gate electrode on the gate dielectric,

wherein the contact plug includes a lower region contacting the source/drain and an upper region on the lower region,

wherein the lower region includes a first lower sidewall and a second lower sidewall opposing each other,

wherein the upper region includes a first upper sidewall and a second upper sidewall opposing each other,

wherein the lower region includes a first lower portion overlapped by the upper region and a second lower portion not overlapped by the upper region in the vertical direction,

wherein the first upper sidewall overlaps the lower region and does not overlap the first and second lower sidewalls in the vertical direction,

wherein an upper end of the isolation layer is at a lower level than an upper end of the source/drain, and

wherein the interlayer insulating structure contacts an upper surface of the second lower portion of the lower region, the first lower sidewall, the second lower sidewall, the first upper sidewall, and the second upper sidewall.

2. The semiconductor device of claim 1 , wherein the upper region of the contact plug extends continuously from the first lower portion of the lower region of the contact plug.

3. The semiconductor device of claim 1 , wherein a thickness of the lower region is greater than a thickness of the upper region.

4. The semiconductor device of claim 1 , wherein the source/drain contacts the plurality of active fins.

5. The semiconductor device of claim 1 , wherein the contact plug is spaced apart from the isolation layer.

6. The semiconductor device of claim 1 , wherein an entire lower surface of the lower region of the contact plug contacts the source/drain.

7. The semiconductor device of claim 1 , wherein the source/drain is formed of an epitaxial layer.

8. The semiconductor device of claim 1 , wherein an upper surface of the isolation layer is at a lower level than a lower surface of the contact plug.

9. The semiconductor device of claim 1 , wherein the contact plug includes a metal layer and a barrier layer,

wherein a first material of the metal layer is different from a second material of the barrier layer, and

wherein the barrier layer contacts a lower surface of the metal layer and at least a portion of a side surface of the metal layer.

10. The semiconductor device of claim 9 , wherein the lower region and the upper region of the contact plug include the metal layer and the barrier layer, and

wherein the metal layer of the upper region extends continuously from the metal layer of the lower region.

11. The semiconductor device of claim 9 , wherein the lower region and the upper region of the contact plug include the metal layer and the barrier layer, and

wherein the barrier layer is not interposed between the metal layer of the upper region and the metal layer of the lower region.

12. The semiconductor device of claim 1 , further comprising a wiring line on the contact plug and the interlayer insulating structure,

wherein the wiring line contacts the upper region of the contact plug.

13. A semiconductor device comprising:

a substrate;

an isolation layer on the substrate;

an active fin on the substrate and extending through the isolation layer in a vertical direction;

a gate structure on the active fin and the isolation layer;

a source/drain on the active fin;

an interlayer insulating layer on the isolation layer;

a contact plug on and contacting the source/drain and extending through the interlayer insulating layer, the contact plug comprising a metal layer and a barrier layer, which is between the metal layer and the source/drain; and

a wiring line on the contact plug and the interlayer insulating layer,

wherein the gate structure includes a gate dielectric and a gate electrode on the gate dielectric,

wherein the contact plug includes a lower region contacting the source/drain and an upper region on the lower region,

wherein the lower region includes a first lower portion of the metal layer overlapped by an upper portion of the metal layer in the upper region and a second lower portion of the metal layer not overlapped by the upper portion of the metal layer in the upper region in the vertical direction,

wherein the upper region extends continuously from the first lower portion of the lower region, and

wherein a lower end of the interlayer insulating layer is at a lower level than a lower end of the contact plug.

14. The semiconductor device of claim 13 , wherein a thickness of the lower region is greater than a thickness of the upper region.

15. The semiconductor device of claim 13 , wherein the wiring line contacts at least a portion of the upper region, and

wherein the wiring line does not overlap the second lower portion of the lower region.

16. The semiconductor device of claim 13 ,

wherein a first material of the metal layer is different from a second material of the barrier layer,

wherein the barrier layer contacts a lower surface of the metal layer and at least a portion of a side surface of the metal layer,

wherein the lower region and the upper region of the contact plug further include the barrier layer, and

wherein the barrier layer is not interposed between the metal layer of the upper region and the metal layer of the lower region.

17. A semiconductor device comprising:

a substrate;

an isolation layer on the substrate;

an active fin on the substrate and extending through the isolation layer in a vertical direction;

a source/drain on the active fin;

a conductive pattern on the active fin and the isolation layer; and

an interlayer insulating structure on the isolation layer,

wherein the conductive pattern includes a lower region and an upper region on the lower region,

wherein the lower region includes a first lower sidewall and a second lower sidewall opposing each other,

wherein the upper region includes a first upper sidewall and a second upper sidewall opposing each other,

wherein the lower region includes a first lower portion overlapped by the upper region and a second lower portion not overlapped by the upper region in the vertical direction,

wherein the first upper sidewall overlaps the lower region and does not overlap the first and second lower sidewalls in the vertical direction,

wherein the upper region of the conductive pattern extends continuously from the first lower portion of the,

wherein a lower end of the interlayer insulating structure is at a lower level than a lower end of the conductive pattern,

wherein an upper end of the isolation layer is at a lower level than an upper end of the source/drain, and

wherein the interlayer insulating structure contacts an upper surface of the second lower portion of the lower region, the first lower sidewall, the second lower sidewall, the first upper sidewall, and the second upper sidewall.

18. The semiconductor device of claim 17 , wherein a thickness of the lower region is greater than a thickness of the upper region.

19. The semiconductor device of claim 17 , wherein a first material of the metal layer is different from a second material of the barrier layer,

wherein the barrier layer contacts a lower surface of the metal layer and at least a portion of a side surface of the metal layer,

wherein the lower region and the upper region of the conductive pattern include the metal layer and the barrier layer, and

wherein the metal layer of the upper region extends continuously from the metal layer of the lower region.

20. The semiconductor device of claim 17 , wherein the conductive pattern includes a metal layer and a barrier layer,

wherein a first material of the metal layer is different from a second material of the barrier layer,

wherein the barrier layer contacts a lower surface of the metal layer and at least a portion of a side surface of the metal layer,

wherein the lower region and the upper region of the conductive pattern include the metal layer and the barrier layer, and

wherein the barrier layer is not interposed between the metal layer of the upper region and the metal layer of the lower region.