FinFET device and method of forming same
A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.
1. A device comprising:
a substrate;
an isolation region over the substrate; and
a semiconductor strip over the substrate and extending through the isolation region, a top surface of the semiconductor strip being above a top surface of the isolation region, wherein the semiconductor strip comprises:
a first portion, the first portion having vertical sidewalls; and
a second portion between the first portion and the substrate, the second portion having sloped sidewalls, the first portion and the second portion being above the top surface of the isolation region.
2. The device of claim 1 , wherein a first height of the first portion of the semiconductor strip is greater than a second height of the second portion of the semiconductor strip.
3. The device of claim 1 , wherein a bottom surface of the second portion of the semiconductor strip is below the top surface of the isolation region.
4. The device of claim 1 , wherein the semiconductor strip comprises SiGe.
5. The device of claim 4 , wherein the first portion of the semiconductor strip has a non-uniform Ge concentration.
6. The device of claim 5 , wherein the non-uniform Ge concentration increases as the first portion of the semiconductor strip extends away from the second portion of the semiconductor strip.
7. The device of claim 5 , wherein the second portion of the semiconductor strip has a uniform Ge concentration.
8. A device comprising:
a substrate;
a semiconductor strip over the substrate, wherein the semiconductor strip comprises:
a first portion, the first portion having a uniform width; and
a second portion between the first portion and the substrate, a width of the second portion decreasing as the second portion extends away from the substrate toward the first portion; and
an isolation region over the substrate and adjacent the semiconductor strip, a top surface of the first portion of the semiconductor strip being above a top surface of the isolation region.
9. The device of claim 8 , wherein the semiconductor strip further comprises a third portion between the second portion and the substrate.
10. The device of claim 9 , wherein the first portion and the second portion of the semiconductor strip comprise a first semiconductor material, and wherein the third portion of the semiconductor strip comprises a second semiconductor material different from the first semiconductor material.
11. The device of claim 10 , wherein the first semiconductor material is SiGe and the second semiconductor material is Si.
12. The device of claim 9 , wherein a bottom surface of the third portion of the semiconductor strip is below the top surface of the isolation region.
13. The device of claim 9 , wherein the third portion of the semiconductor strip has a greater width than the first portion of the semiconductor strip.
14. The device of claim 8 , wherein the semiconductor strip has a non-uniform Ge concentration.
15. A method comprising:
forming semiconductor strips over a substrate;
forming isolation regions between adjacent semiconductor strips;
performing a first etch process on the isolation regions and the semiconductor strips, the first etch process exposing and reshaping first portions of the semiconductor strips to form reshaped first portions of the semiconductor strips, the reshaped first portions of the semiconductor strips having vertical sidewalls;
performing a second etch process on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips; and
performing a third etch process on the second portions of the semiconductor strips to form reshaped second portions of the semiconductor strips, wherein the reshaped second portions of the semiconductor strips have sloped sidewalls.
16. The method of claim 15 , wherein the first etch process is different from the second etch process.
17. The method of claim 16 , wherein the third etch process is different from the first etch process and the second etch process.
18. The method of claim 15 , wherein the reshaped first portions of the semiconductor strips have a first width, and wherein the second portions of the semiconductor strips have a second width greater than the first width.
19. The method of claim 15 , wherein the semiconductor strips comprise SiGe, and wherein the semiconductor strips have non-uniform Ge concentrations.
20. The method of claim 15 , wherein the third etch process is anisotropic.