IP Library › Granted Patent US 11,764,733
Granted Patent B2
US 11,764,733 · App. 17/483,142 · Granted Sep 19, 2023

C-PHY receiver with self-regulated common mode servo loop

Inventors: Shih-Wei Chou (San Diego, CA); Todd Morgan Rasmus (Cary, NC); Ying Duan (San Diego, CA); Abhay Dixit (San Diego, CA)
Assignee: QUALCOMM INCORPORATED
H03F1/0261H03F3/19H03F3/193H04B1/16H04L69/323H05K1/0246H03F2200/451
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Quick Facts
Patent No.
US 11,764,733
App. No.
17/483,142
Granted
Sep 19, 2023
Kind
B2
Abstract

A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Claims (56)

1. A receiving apparatus, comprising:

a terminating network for a three-wire serial bus, each wire of the three-wire serial bus being coupled through a resistance to a common node of the terminating network; and

a feedback circuit comprising:

a first amplifier circuit having an input coupled to the common node;

a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input; and

a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

2. The apparatus of claim 1 , wherein the three-wire serial bus is operated in accordance with a C-PHY protocol.

3. The apparatus of claim 1 , wherein the terminating network comprises:

a capacitance configured to couple the common node to ground.

4. The apparatus of claim 1 , further comprising:

a plurality of differential receivers coupled to different pairs of wires of the three-wire serial bus, wherein the first amplifier circuit has a combination of active devices that matches a corresponding combination of active devices in an amplifier in each of the plurality of differential receivers.

5. The apparatus of claim 1 , wherein the first amplifier circuit and the second amplifier circuit comprise tunable transistors configured to set a voltage level at the common node.

6. The apparatus of claim 1 , wherein the feedback circuit is configured to regulate a voltage level at the common node based on amplitude of the current injected through the common node.

7. The apparatus of claim 1 , wherein a voltage level at the common node is calibrated during transmission of a preamble over the three-wire serial bus in accordance with a C-PHY protocol.

8. The apparatus of claim 7 , wherein the voltage level at the common node is calibrated to be less than half a nominal peak-to-peak voltage of a signal to be transmitted by a transmitter over the three-wire serial bus.

9. The apparatus of claim 1 , further comprising:

a third amplifier configured with an automatic frequency equalization circuit.

10. The apparatus of claim 9 , wherein the third amplifier comprises:

a plurality of P-type metal oxide-semiconductor input transistors; and

a source degeneration circuit.

11. An apparatus, comprising:

means for terminating a three-wire serial bus, configured to couple each wire of the three-wire serial bus through a resistance to a common node; and

means for regulating a common mode voltage level, including a feedback circuit comprising:

a first amplifier circuit having an input coupled to the common node;

a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input; and

a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

12. The apparatus of claim 11 , wherein the three-wire serial bus is operated in accordance with a C-PHY protocol.

13. The apparatus of claim 11 , wherein the means for terminating the three-wire serial bus comprises:

a capacitance configured to couple the common node to ground.

14. The apparatus of claim 11 , further comprising:

means for decoding data from the three-wire serial bus, including a plurality of differential receivers coupled to different pairs of wires of the three-wire serial bus, wherein the first amplifier circuit has a combination of active devices that matches a corresponding combination of active devices in an amplifier in each of the plurality of differential receivers.

15. The apparatus of claim 11 , wherein the first amplifier circuit and the second amplifier circuit comprise tunable transistors configured to set a voltage level at the common node.

16. The apparatus of claim 11 , wherein the feedback circuit is configured to regulate a voltage level at the common node based on amplitude of the current injected through the common node.

17. The apparatus of claim 11 , wherein a voltage level at the common node is calibrated during transmission of a preamble over the three-wire serial bus in accordance with a C-PHY protocol.

18. The apparatus of claim 17 , wherein the voltage level at the common node is calibrated to be less than half a nominal peak-to-peak voltage of a signal to be transmitted by a transmitter over the three-wire serial bus.

19. The apparatus of claim 11 , further comprising:

means for equalizing inputs to a differential receiver.

20. The apparatus of claim 19 , wherein the means for equalizing inputs to the differential receiver comprises:

a plurality of N-type metal-oxide-semiconductor input transistors; and

a source degeneration circuit.

21. A method for regulating a common mode voltage at a receiver, comprising:

providing a terminating network for a three-wire serial bus, each wire of the three-wire serial bus being coupled through a resistance to a common node of the terminating network; and

configuring a feedback circuit that comprises:

a first amplifier circuit having an input coupled to the common node;

a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input; and

a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

22. The method of claim 21 , wherein the three-wire serial bus is operated in accordance with a C-PHY protocol.

23. The method of claim 21 , wherein the terminating network comprises:

a capacitance configured to couple the common node to ground.

24. The method of claim 21 , wherein each of a plurality of differential receivers is coupled to different pairs of wires of the three-wire serial bus, and wherein the first amplifier circuit has a combination of active devices that matches a corresponding combination of active devices in an amplifier in each of the plurality of differential receivers.

25. The method of claim 21 , wherein the first amplifier circuit and the second amplifier circuit comprise tunable transistors configured to set a voltage level at the common node.

26. The method of claim 21 , wherein the feedback circuit is configured to regulate a voltage level at the common node based on amplitude of the current injected through the common node.

27. The method of claim 21 , wherein a voltage level at the common node is calibrated during transmission of a preamble over the three-wire serial bus in accordance with a C-PHY protocol.

28. The method of claim 27 , wherein the voltage level at the common node is calibrated to be less than half a nominal peak-to-peak voltage of a signal to be transmitted by a transmitter over the three-wire serial bus.

29. The method of claim 21 , further comprising:

equalizing inputs to a differential receiver.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2021
From: CHOU, SHIH-WEI; RASMUS, TODD MORGAN; DUAN, YING; DIXIT, ABHAY
To: QUALCOMM INCORPORATED
Reel/Frame 058007/0023 →
Continuity (1)
Related Publication 20230087897A1 · Mar 23, 2023