Time-interleaved analog-to-digital converter and conversion method thereof

1. A slope analog-to-digital converter comprising:

a sample and hold stage configured to sample an analog input signal at a sampling frequency;

a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal; and

a digital logic configured to:

receive a counter value corresponding to a voltage level of the slope signal; and

sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison,

wherein the slope signal is asynchronous to the sampling frequency.

2. The slope analog-to-digital converter according to claim 1 ,

wherein the slope signal is configured to be operable with a slope repetition period T slope ,

wherein the sample and hold stage is further configured to:

sample the analog input signal over a sampling period T smp ; and

hold a voltage level of the sampled analog input signal over a hold period T hold , and

wherein the hold period T hold is greater than the slope repetition period T slope .

3. The slope analog-to-digital converter according to claim 2 ,

wherein the digital logic is further configured to sample the counter value based upon the comparison in a memory block.

4. The slope analog-to-digital converter according to claim 3 ,

wherein the digital logic is further configured to sample the counter value in the memory block on a rising edge or on a falling edge of the comparator output, or

wherein the digital logic is further configured to sample the counter value in the memory block exclusively during the hold period T hold , or

wherein the digital logic is further configured to sample the counter value in the memory block at least once per hold period T hold .

5. The slope analog-to-digital converter according to claim 3 ,

wherein the digital logic is further configured to add or subtract an offset value, preferably a fixed offset value, to the counter value.

6. The slope analog-to-digital converter according to claim 1 ,

wherein the slope analog-to-digital converter is a single-slope analog-to-digital converter, a dual-slope analog-to-digital converter, or a multi-slope analog-to-digital converter.

7. A time-interleaved analog-to-digital converter comprising:

an analog input signal;

a slope generator configured to generate a slope signal having a slope repetition period T slope ;

a global counter configured to generate a counter value corresponding to a voltage level of the slope signal; and

a plurality of slope analog-to-digital converters according to claim 1 ,

wherein the plurality of slope analog-to-digital converters are configured to commonly receive the slope signal and the respective counter value,

wherein the plurality of slope analog-to-digital converters are configured to receive the analog input signal successively in time, and

wherein each of the plurality of slope analog-to-digital converters is configured to generate a digital representation of the analog input signal successively in time using the commonly received slope signal and the respective counter value.

8. The time-interleaved analog-to-digital converter according to claim 7 ,

wherein the time-interleaved analog-to-digital converter further comprises a data aligner configured to combine the corresponding digital representation of the analog input signal from each of the plurality of slope analog-to-digital converters, thereby generating a digital representation of the analog input signal.

9. The time-interleaved analog-to-digital converter according to claim 7 ,

wherein the time-interleaved analog-to-digital converter further comprises a clock generator configured to generate a plurality of clock signals, each having an identical clock period however different phases relative to one another.

10. The time-interleaved analog-to-digital converter according to claim 7 ,

wherein each of the plurality of slope analog-to-digital converters corresponds to a conversion channel whereby the plurality of slope analog-to-digital converters are arranged in parallel to each other, thereby facilitating a plurality of conversion channels operable with a common slope signal.

11. The time-interleaved analog-to-digital converter according to claim 10 ,

wherein the plurality of conversion channels are arranged in an array or a two-dimensional array.

12. The time-interleaved analog-to-digital converter according to claim 11 ,

wherein the time-interleaved analog-to-digital converter further comprises a hierarchical sampling scheme configured to implement time-interleaving in at least two hierarchical levels.

13. The time-interleaved analog-to-digital converter according to claim 12 ,

wherein the hierarchical sampling scheme is further configured to implement time-interleaving in one of at least two hierarchical levels vertically over rows of the two-dimensional array and to implement time-interleaving in one of at least two hierarchical levels horizontally over columns of the two-dimensional array.

14. A method for time-interleaved analog-to-digital conversion comprising:

providing an analog input signal;

providing a plurality of slope analog-to-digital converters according to claim 1 ;

providing the plurality of slope analog-to-digital converters with a common slope signal and a respective counter value;

receiving the analog input signal successively in time by the plurality of slope analog-to-digital converters; and

generating, by each of the plurality of slope analog-to-digital converters, a digital representation of the analog input signal in time succession using the common slope signal and the respective counter value.

15. The method according to claim 14 ,

wherein the method further comprises combining the corresponding digital representation of the analog input signal from each of the plurality of slope analog-to-digital converters, thereby generating a digital representation of the analog input signal.