Display device and method for fabricating the same

1. A display device comprising:

a substrate;

a first conductive layer disposed on the substrate and including a lower light blocking pattern and a first signal line;

a buffer layer disposed on the first conductive layer;

a semiconductor layer disposed on the buffer layer and including a first semiconductor pattern including a channel region of a transistor and a second semiconductor pattern separated from the first semiconductor pattern;

an insulating layer disposed on the semiconductor layer and including an insulating layer pattern;

a second conductive layer disposed on the insulating layer and including a second signal line;

a planarization layer disposed on the second conductive layer; and

a third conductive layer disposed on the planarization layer and including an anode electrode,

wherein the first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and

wherein at least a portion of the second semiconductor pattern is isolated from each of the first signal line and the second signal line, and

wherein the second semiconductor pattern overlaps each of the first signal line and the second signal line in a thickness direction.

2. The display device of claim 1 , further comprising:

a storage capacitor including a first electrode and a second electrode,

wherein the first conductive layer includes the first electrode of the storage capacitor,

wherein the second conductive layer includes the second electrode of the storage capacitor, and

wherein a distance in the thickness direction between the first signal line and the second signal line is greater than a distance in the thickness direction between the first electrode and the second electrode of the storage capacitor.

3. The display device of claim 1 , wherein the anode electrode is connected to the lower light blocking pattern through a first contact hole passing through the planarization layer and the buffer layer, and is connected to the first semiconductor pattern of the transistor through a second contact hole passing through the planarization layer.

4. The display device of claim 1 , wherein the third conductive layer further includes a sub conductive pattern separated from the anode electrode, and the sub conductive pattern electrically connects the first signal line to the first semiconductor pattern of the transistor.

5. The display device of claim 4 , wherein the sub conductive pattern contacts the first signal line through a third contact hole passing through the planarization layer and the buffer layer, and contacts the first semiconductor pattern of the transistor through a fourth contact hole passing through the planarization layer.

6. The display device of claim 1 , wherein the first signal line is one of a first power line and a data line, and the second signal line is a scan line.

7. The display device of claim 6 , wherein the second signal line extends in a first direction, the first signal line extends in a second direction intersecting the first direction, and the first signal line and the second signal line intersect each other in an overlap region.

8. The display device of claim 7 , wherein a length of the second semiconductor pattern in the first direction is equal to or greater than a width of the first signal line in the first direction, and

wherein a length of the second semiconductor pattern in the second direction is equal to or greater than a width of the second signal line in the second direction.

9. The display device of claim 1 , wherein an overlap region where the first signal line and the second signal line overlap each other completely overlaps the second semiconductor pattern in the thickness direction.

10. The display device of claim 9 , wherein at least a portion of the insulating layer pattern is disposed in the overlap region and overlaps the second semiconductor pattern in the thickness direction.