Neural network mapping method and apparatus

1. A neural network mapping method applied to a chip comprising a plurality of processing elements, comprising:

mapping a calculation task for a preset feature map of each network layer in a plurality of network layers in a convolutional neural network to at least one processing element of the chip;

acquiring a number of phases needed by the plurality of processing elements in the chip for completing the calculation task, and performing a first stage of balancing on the number of phases of the plurality of processing elements; and

mapping, based on the number of the phases of the plurality of processing elements obtained after the first stage of balancing, the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip,

wherein performing the first stage of balancing on the number of phases of the plurality of processing elements comprises:

determining whether a descent direction of the first stage of balancing exists; and

calculating, in response to a determination result that the descent direction of the first stage of balancing exists, a first-stage balancing reference, and performing the first stage of balancing according to the first-stage balancing reference.

2. The method of claim 1 , wherein determining whether the descent direction of the first stage of balancing exists comprises:

in a case where it is determined that performing the first stage of balancing causes a value of 1 minus a global utilization rate of the plurality of processing elements to decrease, determining that the descent direction of the first stage of balancing exists.

3. The method of claim 2 , wherein determining whether the descent direction of the first stage of balancing exists comprises:

acquiring a preset balancing vector, and determining whether the descent direction of the first stage of balancing exists based on the preset balancing vector.

4. The method of claim 3 , wherein a formula of the preset balancing vector is:

p =( pr,px,pf,py,pw )

wherein p is the preset balancing vector;

pr is configured to adjust a number of Multiply Accumulate operations (MACs) of a processing element in one phase in a reduction loop;

px is configured to adjust the number of phases of a processing element in a horizontal direction;

pf is configured to adjust the number of MACs of a processing element in one phase in an output feature loop;

py is configured to adjust the number of phases of a processing element in a vertical direction; and

pw is configured to adjust the number of phases and the number of MACs in the phases.

5. The method of claim 1 , wherein calculating the first-stage balancing reference comprises:

acquiring loads of the plurality of processing elements, setting a reference load of balancing based on the loads of the plurality of processing elements, and taking the reference load as the first-stage balancing reference.

6. The method of claim 4 , wherein performing the first stage of balancing according to the first-stage balancing reference comprises:

extracting a first balancing vector from the preset balancing vector, and performing the first stage of balancing by using the first balancing vector according to the first-stage balancing reference;

wherein p 1 =(px, py, pw), and p1 is the first balancing vector,

px is configured to adjust the number of phases of a processing element in the horizontal direction,

py is configured to adjust the number of phases of a processing element in the vertical direction, and pw is configured to adjust the number of phases and the number of MACs in the phases.

7. The method of claim 1 , wherein after mapping, based on the number of the phases of the plurality of processing elements obtained after the first stage of balancing, the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip, the method further comprises:

acquiring a number of MACs in the plurality of phases, and performing a second stage of balancing based on the number of MACs in the plurality of phases; and

mapping the calculation task for the preset feature map of the plurality of network layers in the convolutional neural network to at least one processing element of the chip subjected to the second stage of balancing.

8. The method of claim 7 , wherein acquiring the number of MACs in the plurality of phases, and performing the second stage of balancing based on the number of MACs in the plurality of phases comprises:

acquiring the number of MACs in each phase, and determining whether a descent direction of the second stage of balancing exists; in a case where it is determined that performing the second stage of balancing causes the value of 1 minus the global utilization rate of the plurality of processing elements to decrease, determining that the descent direction of the second stage of balancing exists; and

calculating, in response to a determination result that the descent direction of the second stage of balancing exists, a second-stage balancing reference, and performing the second stage of balancing according to the second-stage balancing reference.

9. The method of claim 7 , after mapping the calculation task for the preset feature map of the plurality of network layers in the convolutional neural network to at least one processing element of the chip subjected to the second stage of balancing, the method further comprises:

performing an iteration of the first stage of balancing and the second stage of balancing.

10. A neural network mapping apparatus, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements a neural network mapping method applied to a chip comprising a plurality of processing elements, and wherein the method comprises:

mapping a calculation task for a preset feature map of each network layer in a plurality of network layers in a convolutional neural network to at least one processing element of the chip;

acquiring a number of phases needed by the plurality of processing elements in the chip for completing the calculation task, and performing a first stage of balancing on the number of phases of the plurality of processing elements; and

mapping, based on the number of the phases of the plurality of processing elements obtained after the first stage of balancing, the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip,

wherein performing the first stage of balancing on the number of phases of the plurality of processing elements comprises:

determining whether a descent direction of the first stage of balancing exists; and

calculating, in response to a determination result that the descent direction of the first stage of balancing exists, a first-stage balancing reference, and performing the first stage of balancing according to the first-stage balancing reference.

11. A non-transitory computer-readable storage medium, storing a computer program, wherein the program is executed by a processor to perform a neural network mapping method applied to a chip comprising a plurality of processing elements, comprising:

mapping a calculation task for a preset feature map of each network layer in a plurality of network layers in a convolutional neural network to at least one processing element of the chip;

acquiring a number of phases needed by the plurality of processing elements in the chip for completing the calculation task, and performing a first stage of balancing on the number of phases of the plurality of processing elements; and

mapping, based on the number of the phases of the plurality of processing elements obtained after the first stage of balancing, the calculation task for the preset feature map of each network layer in the plurality of network layers in the convolutional neural network to at least one processing element of the chip,

wherein performing the first stage of balancing on the number of phases of the plurality of processing elements comprises:

determining whether a descent direction of the first stage of balancing exists; and

calculating, in response to a determination result that the descent direction of the first stage of balancing exists, a first-stage balancing reference, and performing the first stage of balancing according to the first-stage balancing reference.