Reduced-leakage apparatus for sampling electrical signals and associated methods
An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.
1. An apparatus, comprising:
first and second metal oxide semiconductor field effect transistors (MOSFETs) coupled in cascade to selectively provide power to a circuit; and
a native transistor coupled to provide a gate voltage of the second MOSFET and wherein a gate of the native transistor is driven by a drain of the second MOSFET.
2. The apparatus according to claim 1 , wherein the native transistor is biased to reduce a gate induced drain leakage (GIDL) current of the first MOSFET.
3. The apparatus according to claim 2 , wherein a gate of the native transistor is coupled to a drain of the second MOSFET and wherein a source of the native transistor is coupled to the gate of the second MOSFET.
4. The apparatus according to claim 1 , wherein a gate voltage of the first MOSFET is changed in order to selectively provide power to the circuit.
5. The apparatus according to claim 4 , wherein the gate voltage of the first MOSFET is changed to a ground voltage to provide power to the circuit.
6. The apparatus according to claim 4 , wherein the gate voltage of the first MOSFET is changed to a supply voltage to power down the circuit.
7. The apparatus according to claim 1 , wherein to power down the circuit a source voltage of the native transistor is applied to a gate of the second MOSFET to turn off the second MOSFET.
8. The apparatus according to claim 7 , wherein to power down the circuit a supply voltage is applied to a gate of the first MOSFET to turn off the first MOSFET.
9. The apparatus according to claim 1 , wherein a source of the native transistor is coupled to a gate of the second MOSFET.
10. An apparatus, comprising:
first and second metal oxide semiconductor field effect transistors (MOSFETs) coupled in cascade to selectively provide power to a circuit and
a native transistor coupled to provide a gate voltage of the second MOSFET,
wherein a source of the second MOSFET has a voltage equal to a threshold voltage of the native transistor plus a threshold voltage of the second MOSFET.
11. A method of selectively providing power to a circuit, the method comprising:
using first and second metal oxide semiconductor field effect transistors (MOSFETs) coupled in cascade to selectively provide power to the circuit;
using a native transistor to provide a gate voltage of the second MOSFET; and
driving a gate of the native transistor by a drain of the second MOSFET.
12. The method according to claim 11 , further comprising biasing the native transistor to reduce a gate induced drain leakage (GIDL) current of the first MOSFET.
13. The method according to claim 12 , wherein a gate of the native transistor is coupled to a drain of the second MOSFET and wherein a source of the native transistor is coupled to the gate of the second MOSFET.
14. The method according to claim 11 , further comprising changing a gate voltage of the first MOSFET to selectively provide power to the circuit.
15. The method according to claim 14 , wherein changing the gate voltage of the first MOSFET to selectively provide power to the circuit comprises changing the gate voltage of the first MOSFET to a ground voltage to provide power to the circuit.
16. The method according to claim 14 , wherein changing the gate voltage of the first MOSFET to selectively provide power to the circuit comprises changing the gate voltage of the first MOSFET to a supply voltage to power down the circuit.
17. The method according to claim 11 , further comprising powering down the circuit by applying a source voltage of the native transistor to a gate of the second MOSFET to turn off the second MOSFET.
18. The method according to claim 17 , wherein powering down the circuit further comprises applying a supply voltage to a gate of the first MOSFET to turn off the first MOSFET.
19. The method according to claim 11 , wherein a source of the native transistor is coupled to a gate of the second MOSFET.
20. The method according to claim 19 , wherein a source of the second MOSFET has a voltage equal to a threshold voltage of the native transistor plus a threshold voltage of the second MOSFET.