Method of manufacturing a semiconductor memory device having capacitor electrodes and a vertical contact plug

1. A method of manufacturing a semiconductor memory device, the method comprising:

forming a lower insulating layer in which an interconnection pattern and a lower conductive pattern are embedded;

forming a stack structure over the lower insulating layer, the stack structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a first direction;

forming a first opening and a second opening to penetrate the stack structure and the lower insulating layer and expose the lower conductive pattern;

forming a conductive material in the first and second openings, wherein a thickness of the conductive material is controlled to fill the second opening and to open a central region of the first opening;

separating the conductive material into a first capacitor electrode on a surface of the first opening and a vertical contact plug filling the second opening;

forming a dielectric layer over a surface of the first capacitor electrode; and

forming a second capacitor electrode over the dielectric layer to fill the first opening.

2. The method according to claim 1 , further comprising:

forming an insulating layer covering the stack structure, the dielectric layer, the vertical contact plug, and the second capacitor electrode;

forming capacitor contact structures that penetrate the insulating layer and that are coupled to the vertical contact plug and the second capacitor electrode, respectively; and

forming upper conductive patterns coupled to the capacitor contact structures, respectively.

3. The method according to claim 1 , further comprising:

forming a third opening to expose the interconnection pattern while the first opening and the second opening are formed; and

filling the third opening with a peripheral contact plug while the first capacitor electrode is formed.

4. The method according to claim 1 , further comprising, before the first opening and the second opening are formed:

forming a channel hole penetrating a cell array area of the stack structure;

forming a memory layer over a surface of the channel hole;

forming a channel structure over the memory layer to fill the channel hole;

forming a slit penetrating the cell array area of the stack structure; and

replacing portions of respective sacrificial insulating layers disposed in the cell array area of the stack structure with conductive patterns through the slit.

5. A method of manufacturing a semiconductor memory device, the method comprising:

forming a lower insulating layer in which an interconnection pattern and a lower conductive pattern are embedded;

forming a stack structure over the lower insulating layer, the stack structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a first direction;

forming a first opening and a second opening to penetrate the stack structure and the lower insulating layer and expose the lower conductive pattern;

forming a first capacitor electrode on a surface of the first opening;

forming a dielectric layer over a surface of the first capacitor electrode; and

forming a second capacitor electrode over the dielectric layer to fill the first opening,

wherein the second opening is filled with a vertical contact plug while the first capacitor electrode is formed,

wherein the dielectric layer extends to cover the vertical contact plug, and

wherein the method further comprises, before the second capacitor electrode is formed, forming a contact hole penetrating the dielectric layer and exposing the vertical contact plug.

6. The method according to claim 5 , further comprising, while the second capacitor electrode is formed, filling the contact hole with a lower plug.

7. A method of manufacturing a semiconductor memory device, the method comprising:

forming a lower insulating layer in which an interconnection pattern and a lower conductive pattern are embedded;

forming a semiconductor structure over the lower insulating layer;

forming first and second insulating patterns penetrating the semiconductor structure and overlapping the lower conductive pattern;

forming a stack structure over the lower insulating layer, the stack structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a first direction;

forming a first opening and a second opening to penetrate the stack structure and the lower insulating layer and expose the lower conductive pattern;

forming a first capacitor electrode on a surface of the first opening;

forming a dielectric layer over a surface of the first capacitor electrode; and

forming a second capacitor electrode over the dielectric layer to fill the first opening,

wherein the second opening is filled with a vertical contact plug while the first capacitor electrode is formed.

8. The method according to claim 7 , wherein forming the first opening and the second opening comprises:

etching the first and second insulating patterns to expose the lower conductive pattern.