IP Library › Granted Patent US 11,770,636
Granted Patent B2
US 11,770,636 · App. 16/928,698 · Granted Sep 26, 2023

Optical sensor, method of manufacturing the same, and display device including the same

Inventors: Jung Ha Son (Yongin-si, KR); Gee Bum Kim (Yongin-si, KR); Sang Woo Kim (Yongin-si, KR); Ki June Lee (Yongin-si, KR); Jae Ik Lim (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H04N25/76H01L27/14609H04N25/705
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Quick Facts
Patent No.
US 11,770,636
App. No.
16/928,698
Granted
Sep 26, 2023
Kind
B2
Abstract

An optical sensor including: a substrate; a circuit element layer disposed on the substrate and including a circuit element; and a photoelectric element layer including a photoelectric element, a self-assembled monolayer, and a bias electrode connected to the photoelectric element, wherein the photoelectric element is connected to the circuit element, and wherein the self-assembled monolayer is disposed on the photoelectric element.

Claims (49)

1. An optical sensor comprising:

a substrate;

a circuit element layer disposed on the substrate and including a circuit element; and

a photoelectric element layer including a photoelectric element, a self-assembled monolayer, and a bias electrode connected to the photoelectric element, wherein the photoelectric element is connected to the circuit element,

wherein the self-assembled monolayer is disposed on the photoelectric element,

wherein a protective layer is disposed between the photoelectric element and a portion of the bias electrode, and

wherein the photoelectric element includes:

a lower electrode connected to the circuit element;

a P-Intrinsic-N(PIN) layer disposed on the lower electrode; and

an upper electrode disposed on the PIN layer and connected to the bias electrode.

2. The optical sensor of claim 1 ,

wherein the photoelectric element layer further includes the protective layer covering the upper electrode, and

wherein the bias electrode is formed on the protective layer and is connected to the upper electrode through a contact hole formed in the protective layer.

3. The optical sensor of claim 2 , wherein the self-assembled monolayer is formed between the protective layer and the bias electrode.

4. The optical sensor of claim 1 , wherein the PIN layer includes:

an N-type semiconductor layer disposed on the lower electrode;

an I-type semiconductor layer formed on the N-type semiconductor layer; and

a P-type semiconductor layer formed on the I-type semiconductor layer.

5. The optical sensor of claim 1 , wherein the circuit element layer includes:

an active pattern having a channel region, and a source region and a drain region on opposing sides of the channel region, respectively;

a gate insulating layer covering the active pattern;

a gate electrode formed on the gate insulating layer, wherein at least a part of the gate electrode overlaps the channel region;

an interlayer insulating layer covering the gate electrode;

a source electrode and a drain electrode formed on the interlayer insulating layer and respectively connected to the source region and the drain region through contact holes; and

a protective layer covering the source electrode and the drain electrode.

6. The optical sensor of claim 1 , further comprising:

a planarization layer formed on the photoelectric element layer.

7. A display device comprising:

a display panel including pixels; and

an optical sensor disposed on the display panel and including a plurality of sensor pixels,

wherein each of the plurality of sensor pixels includes:

a first substrate;

a first circuit element layer disposed on the first substrate and including a first circuit element configuring the plurality of sensor pixels; and

a photoelectric element layer including a photoelectric element, a self-assembled monolayer, and a bias electrode connected to the photoelectric element, wherein the photoelectric element s connected to the first circuit element,

wherein the bias electrode overlaps the self-assembled monolayer, and

wherein the photoelectric element includes:

a lower electrode connected to the first circuit element;

a P-Intrinsic-N(PIN) layer disposed on the lower electrode; and

an upper electrode disposed on the PIN layer and connected to the bias electrode.

8. The display device of claim 7 ,

wherein the photoelectric element layer further includes a first protective layer covering the upper electrode, and

wherein the bias electrode is formed on the first protective layer and is connected to the upper electrode through a contact hole formed in the first protective layer.

9. The display device of claim 8 , wherein the self-assembled monolayer is formed between the first protective layer and the bias electrode.

10. The display device of claim 7 , wherein the display panel includes:

a second substrate;

a second circuit element layer disposed on the second substrate and including a second circuit element configuring the pixels;

a light emitting element layer formed on the second circuit element layer and including light emitting elements forming the plurality of pixels; and

a second protective layer formed on the light emitting element layer.

11. The display device of claim 10 , wherein the display panel further includes a light blocking layer disposed between the second substrate and the second circuit element layer and including openings through which incident light passes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: SON, JUNG HA; KIM, GEE BUM; KIM, SANG WOO; LEE, KI JUNE; LIM, JAE IK
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 053206/0227 →
Priority Claims (1)
KR 10-2019-0091281 · Jul 26, 2019 · national
Continuity (1)
Related Publication 20210029318A1 · Jan 28, 2021