Thin film transistor random access memory
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.
1. An apparatus, comprising:
a memory cell comprising a plurality of transistors configured to store a logic state, the plurality of transistors comprising:
a first set of one or more transistors each comprising:
a respective first gate portion comprising a first conductor formed above a substrate; and
a respective first channel portion comprising a pillar formed above the substrate and configured to be activated based at least in part on a voltage of the respective first gate portion; and
a second set of one or more transistors each comprising:
a respective second gate portion comprising a second conductor formed above the substrate; and
a respective second channel portion comprising a doped portion of the substrate that is configured to be activated based at least in part on a voltage of the respective second gate portion.
2. The apparatus of claim 1 , wherein the respective first channel portion of each transistor of the first set of one or more transistors comprises a plurality of pillars formed above the substrate.
3. The apparatus of claim 1 , wherein the pillars of the first channel portions of all of the first set of one or more transistors have a common height dimension relative to the substrate.
4. The apparatus of claim 1 , wherein the first set of one or more transistors comprises:
a first subset of transistors, wherein the pillar of the respective first channel portion of each transistor of the first subset of transistors has a first height dimension relative to the substrate; and
a second subset of transistors, wherein the pillar of the respective first channel portion of each transistor of the second subset of transistors has a second height dimension relative to the substrate.
5. The apparatus of claim 1 , wherein each transistor of the second set of one or more transistors is configured in a planar transistor arrangement.
6. The apparatus of claim 1 , wherein:
each transistor of the first set of one or more transistors is configured as an n-type transistor; and
each transistor of the second set of one or more transistors is configured as a p-type transistor.
7. The apparatus of claim 6 , wherein:
the first set of one or more transistors comprises four n-type transistors; and
the second set of one or more transistors comprises two p-type transistors.
8. A method, comprising:
forming a memory cell comprising a plurality of transistors configured to store a logic state, wherein forming the memory cell comprises:
forming a first set of one or more transistors each comprising:
a respective first gate portion comprising a first conductor formed above a substrate; and
a respective first channel portion comprising a pillar formed above the substrate and configured to be activated based at least in part on a voltage of the respective first gate portion; and
forming a second set of one or more transistors each comprising:
a respective second gate portion comprising a second conductor formed above the substrate; and
a respective second channel portion comprising a doped portion of the substrate that is configured to be activated based at least in part on a voltage of the respective second gate portion.
9. The method of claim 8 , wherein the respective first channel portion of each transistor of the first set of one or more transistors comprises a plurality of pillars formed above the substrate.
10. The method of claim 8 , wherein the pillars of the channel portions of all of the first set of one or more transistors are formed with a common height dimension relative to the substrate.
11. The method of claim 8 , wherein the first set of one or more transistors comprises:
a first subset of transistors, wherein the pillar of the respective first channel portion of each transistor of the first subset of transistors is formed with a first height dimension relative to the substrate; and
a second subset of transistors, wherein the pillar of the respective first channel portion of each transistor of the second subset of transistors is formed with a second height dimension relative to the substrate.
12. The method of claim 8 , wherein each transistor of the second set of one or more transistors is formed in a planar transistor arrangement.
13. The method of claim 8 , wherein:
each transistor of the first set of one or more transistors is formed as an n-type transistor; and
each transistor of the second set of one or more transistors is formed as a p-type transistor.
14. The method of claim 13 , wherein:
the first set of one or more transistors comprises four n-type transistors; and
the second set of one or more transistors comprises two p-type transistors.