IP Library › Granted Patent US 11,775,215
Granted Patent B2
US 11,775,215 · App. 17/395,027 · Granted Oct 3, 2023

Storage device with host-controlled operation mode, electronic system including the same, and method of operating the same

Inventors: Byung Ki Lee (Hwaseong-si, KR); Joo Young Hwang (Suwon-si, KR); Jun Hee Kim (Suwon-si, KR); Keun San Park (Hwaseong-si, KR); Je Kyeom Jeon (Siheung-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/0659G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 11,775,215
App. No.
17/395,027
Granted
Oct 3, 2023
Kind
B2
Abstract

Provided is a storage device including a non-volatile memory including a first memory block and a second memory block different from the first memory block, and a memory controller configured to receive, from a host, a first write mode command corresponding to the first memory block and a second write mode command corresponding to the second memory block, control the first memory block to perform a first write operation according to the first write mode command, and control the second memory block to perform a second write operation according to the second write mode command, both the first write operation and the second write operation being sequential write operations.

Claims (59)

1. A storage device comprising:

a non-volatile memory including a first memory block and a second memory block different from the first memory block; and

a memory controller configured to,

receive, from a host, a first write mode command corresponding to the first memory block and a second write mode command corresponding to the second memory block,

control the first memory block to perform a first write operation according to the first write mode command, the first write operation including sequentially writing first data to the first memory block, and

control the second memory block to perform a second write operation according to the second write mode command, the second write operation including sequentially writing second data to the second memory block, wherein

the first memory block stores first write mode data based on the first write mode command, the first write mode data indicating a first write mode among a plurality of write modes, and

the second memory block stores second write mode data based on the second write mode command, the second write mode data indicating a second write mode among the plurality of write modes.

2. The storage device of claim 1 , wherein the memory controller is not configured to perform garbage collection.

3. The storage device of claim 2 , wherein the memory controller is configured to:

receive a first write command after receiving the first write mode command, the first write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one among the plurality of write modes; and

control the first memory block to store the first write mode data and the temporary write mode data in response to receiving the first write command.

4. The storage device of claim 1 , wherein the memory controller is configured to:

control the first memory block to perform the first write operation according to a single-level cell write mode; and

control the second memory block to perform the second write operation according to a multiple level cell write mode.

5. The storage device of claim 4 , wherein the multiple level cell write mode includes a multi-level cell write mode, a triple-level cell write mode, or a quadruple-level cell write mode.

6. The storage device of claim 1 , wherein the memory controller is configured to:

receive a first write command after receiving the first write mode command, the first write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one among the plurality of write modes; and

control the first memory block to perform a third write operation according to the first write command and the temporary write mode data.

7. The storage device of claim 6 , wherein the memory controller is configured to:

receive a write mode reset command corresponding to the first memory block after receiving the first write command; and

control the first memory block to perform another write operation according to the first write mode command after receiving the write mode reset command.

8. The storage device of claim 1 , wherein the memory controller is configured to perform a wear leveling operation in the same memory block unit as the first memory block and the second memory block.

9. The storage device of claim 1 , wherein the memory controller is configured to:

receive a report command from the host; and

control the non-volatile memory to read the first write mode data and the second write mode data in response to receiving the report command.

10. An electronic system comprising:

a non-volatile memory including a first memory block and a second memory block;

a host including a file system having a first zone and a second zone, the first zone corresponding to the first memory block, and the second zone corresponding to the second memory block, the host configured to,

provide a first write mode command corresponding to the first memory block to a memory controller,

provide a second write mode command corresponding to the second memory block to the memory controller,

provide a first write command corresponding to the first zone to the memory controller, and

provide a second write command corresponding to the second zone to the memory controller; and

the memory controller configured to,

control the first memory block to perform a first write operation according to the first write command and the first write mode command, the first write operation including sequentially writing first data to the first memory block,

control the second memory block to perform a second write operation according to the second write command and the second write mode command, the second write operation including sequentially writing second data to the second memory block,

receive a third write command after receiving the first write mode command, the third write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one among a plurality of write modes; and

control the first memory block to perform a third write operation according to the third write command and the temporary write mode data in response to receiving the third write command.

11. The electronic system of claim 10 , wherein the memory controller is not configured to perform garbage collection.

12. The electronic system of claim 11 , wherein the host is configured to perform the garbage collection from the first zone to the second zone.

13. The electronic system of claim 12 , wherein the memory controller is configured to:

control the first memory block to perform the first write operation according to a single-level cell write mode; and

control the second memory block to perform the second write operation according to a multiple level cell write mode.

14. The electronic system of claim 10 , wherein the memory controller is configured to perform a wear leveling operation in the same memory block unit as the first memory block and the second memory block.

15. A method of operating a storage device, the method comprising:

receiving a first write mode command corresponding to a first memory block, the first memory block corresponding to a first zone in a file system;

receiving a second write mode command corresponding to a second memory block, the second memory block corresponding to a second zone in the file system, and the second zone being different from the first zone;

receiving a first write command corresponding to the first zone;

performing a first write operation on the first memory block according to the first write command and the first write mode command, the first write operation including sequentially writing first data to the first memory block;

receiving a second write command corresponding to the second zone;

performing a second write operation on the second memory block according to the second write command and the second write mode command, the second write operation including sequentially writing second data to the second memory block;

receiving a third write command after the receiving the first write mode command, the third write command including temporary write mode data corresponding to the first memory block, and the temporary write mode data indicating one among a plurality of write modes; and

performing a third write operation according to the third write command and the temporary write mode data.

16. The method of claim 15 , further comprising:

receiving a write mode reset command corresponding to the first memory block after the receiving the third write command; and

performing another a write operation on the first memory block according to the first write mode command in response to the receiving the write mode reset command.

17. The method of claim 15 , further comprising:

storing first write mode data in the first memory block based on the first write mode command, the first write mode data indicating a first write mode among a plurality of write modes; and

storing second write mode data in the second memory block based on the second write mode command, the second write mode data indicating a second write mode among the plurality of write modes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2021
From: LEE, BYUNG KI; HWANG, JOO YOUNG; KIM, JUN HEE; PARK, KEUN SAN; JEON, JE KYEOM
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 057157/0459 →
Priority Claims (1)
KR 10-2020-0152806 · Nov 16, 2020 · national
Continuity (1)
Related Publication 20220156008A1 · May 19, 2022