IP Library › Granted Patent US 11,776,482
Granted Patent B2
US 11,776,482 · App. 17/699,943 · Granted Oct 3, 2023

Scan driver for a display device with reduced degradation of transistors

Inventors: Jong Hee Kim (Yongin-si, KR); Soo Yeon Lee (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
G09G3/3266G09G3/3677G09G2310/08
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Quick Facts
Patent No.
US 11,776,482
App. No.
17/699,943
Granted
Oct 3, 2023
Kind
B2
Abstract

A scan driver for a display device includes a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage includes: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.

Claims (10)

1. A scan driver for a display device comprising:

a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage,

wherein the first scan stage comprises:

a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line;

a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node;

a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line;

a fourth transistor including a gate electrode coupled to an other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node;

a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; and

a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node,

wherein the first node is directly coupled to a first carry line.

Priority Claims (1)
KR 10-2019-0012204 · Jan 30, 2019 · national
Continuity (2)
Division 16744009 · Jan 15, 2020
Related Publication 20220319436A1 · Oct 6, 2022