Memory device including massbit counter and method of operating the same
A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.
1. An apparatus comprising:
a plurality of memory cells; and
a controller coupled to the plurality of memory cells and configured to:
perform a first programming loop including programming each of the plurality of memory cells to one of a plurality of first program states and verifying that one or more of the plurality of memory cells has a threshold voltage that is equal to or greater than one of a plurality of first verifying voltages corresponding to the plurality of first program states
adjusting at least one of a sampling rate or a scaling ratio based on a result of the verifying that one or more of the plurality of memory cells has a threshold voltage that is equal to or greater than one of the plurality of first verifying voltages corresponding to the plurality of first program states, and
perform a second programming loop including programming each of the plurality of memory cells to one of a plurality of second program states and verifying, using the at least one adjusted sampling rate or scaling ratio, that at least one of the plurality of memory cells has the threshold voltage that is equal to or greater than one of a plurality of second verify voltages corresponding to the plurality of second program states.
2. The apparatus of claim 1 , wherein the controller iteratively programs each of the plurality of memory cells to one of the plurality of first program states, and iteratively programs each of the plurality of memory cells to one of the plurality of second program states.
3. The apparatus of claim 1 , wherein the first programming loop ends before all of the plurality of memory cells are verified such that at least one of the plurality of memory cells are below one of the plurality of first verify voltages.
4. The apparatus of claim 1 , wherein the controller counts the number of the plurality of memory cells having the threshold voltage that is equal to or greater than one of the plurality of first verify voltages, and continues programming, verifying and counting until the number is greater than a threshold number.
5. The apparatus of claim 4 , wherein the controller determines the threshold number for each of the plurality of memory cells based on which of the plurality of second program states corresponds with each of the plurality of memory cells.
6. The apparatus of claim 1 , wherein
the controller selects one of a plurality of word lines and sets a first programming voltage for the first programming loop,
the controller applies the first programming voltage to the selected one of the plurality of word lines, and
the controller selects a first verification signal for one of the plurality of first program states and applies the first verification signal to the selected one of the plurality of word lines.
7. The apparatus of claim 6 , wherein
the controller selects one of the plurality of word lines and sets a second programming voltage for the second programming loop,
the controller applies the second programming voltage to the selected one of the plurality of word lines, and
the controller selects a second verification signal for one of the plurality of second program states and applies the second verification signal to the selected one of the plurality of word lines.
8. A controller in communication with a plurality of memory cells of a memory apparatus, the controller configured to:
instruct the memory apparatus to perform a first programming loop including iteratively programming each of the plurality of memory cells to one of a plurality of first program states and to verify that one or more of the plurality of memory cells has a threshold voltage above one of a plurality of first verify voltages corresponding to the plurality of first program states;
adjust at least one of a sampling rate or a scaling ratio based on a result of the verifying that one or more of the plurality of memory cells has the threshold voltage that is equal to or greater than one of a plurality of first verifying voltages corresponding to the plurality of first program states; and
instruct the memory apparatus to perform a second programming loop including iteratively programming each of the plurality of memory cells to one of a plurality of second program states and to verify, using the at least one adjusted sampling rate or scaling ratio, that at least one of the plurality of memory cells has the threshold voltage above one of a plurality of second verify voltages corresponding to the plurality of second program states.
9. The controller of claim 8 , wherein the first programming loop ends before all of the plurality of memory cells are verified such that at least one of the plurality of memory cells are below one of the plurality of first verify voltages.
10. The controller of claim 8 , wherein the controller counts the number of the plurality of memory cells having the threshold voltage above one of the plurality of first verify voltages, and continues programming, verifying and counting until the number is greater than a threshold number.
11. The controller of claim 10 , wherein the controller determines the threshold number for each of the plurality of memory cells based on which of the plurality of second program states corresponds with each of the plurality of memory cells.
12. The controller of claim 8 , wherein
the controller selects one of a plurality of word lines and sets a first programming voltage for the first programming loop,
the controller applies the first programming voltage to the selected one of the plurality of word lines, and
the controller selects a first verification signal for one of the plurality of first program states and applies the first verification signal to the selected one of the plurality of word lines.
13. The controller of claim 12 , wherein
the controller selects one of the plurality of word lines and sets a second programming voltage for the second programming loop,
the controller applies the second programming voltage to the selected one of the plurality of word lines, and
the controller selects a second verification signal for one of the plurality of second program states and applies the second verification signal to the selected one of the plurality of word lines.
14. A method of operating a memory apparatus including a plurality of memory cells, the method comprising:
performing a first programming loop including programming each of the plurality of memory cells to one of a plurality of first program states and verifying that one or more of the plurality of memory cells has a threshold voltage above one of a plurality of first verify voltages corresponding to the plurality of first program states;
adjusting at least one of a sampling rate or a scaling ratio based on a result of the verifying that one or more of the plurality of memory cells has the threshold voltage that is equal to or greater than one of a plurality of first verifying voltages corresponding to the plurality of first program states; and
performing a second programming loop including programming each of the plurality of memory cells to one of a plurality of second program states and verifying, using the at least one adjusted sampling rate or scaling ratio, that at least one of the plurality of memory cells has the threshold voltage above one of a plurality of second verify voltages corresponding to the plurality of second program states.
15. The method of claim 14 , wherein the first programming loop includes iteratively programming each of the plurality of memory cells to one of the plurality of first program states, and iteratively programming each of the plurality of memory cells to one of the plurality of second program states.
16. The method of claim 14 , wherein the first programming loop ends before all of the plurality of memory cells are verified such that at least one of the plurality of memory cells are below one of the plurality of first verify voltages.
17. The method of claim 14 , further comprising:
counting the number of the plurality of memory cells having the threshold voltage that is greater than one of the plurality of first verify voltages; and
continuing programming, verifying and counting until the number is greater than a threshold number.
18. The method of claim 17 , further comprising determining the threshold number for each of the plurality of memory cells based on which of the plurality of second program states corresponds with each of the plurality of memory cells.
19. The method of claim 14 , further comprising:
selecting one of a plurality of word lines and setting a first programming voltage for the first programming loop;
applying the first programming voltage to the selected one of the plurality of word lines; and
selecting a first verification signal for one of the plurality of first program states and applying the first verification signal to the selected one of the plurality of word lines.
20. The method of claim 19 , further comprising:
selecting one of the plurality of word lines and setting a second programming voltage for the second programming loop;
applying the second programming voltage to the selected one of the plurality of word lines; and
selecting a second verification signal for one of the plurality of second program states and applying the second verification signal to the selected one of the plurality of word lines.