Semiconductor memory device

1. A method of manufacturing a semiconductor device, comprising:

forming word lines extending in a first direction in a semiconductor substrate;

forming bit line structures extending in a second direction, each of the bit line structures comprising a conductive pattern, and a hard mask pattern on the conductive pattern;

forming spacer structures on sidewalls of each of the bit line structures, each of the spacer structures comprising first and second spacers and a first sacrificial spacer between the first and second spacers;

forming insulating patterns spaced apart from each other between adjacent ones of the bit line structures to define a contact hole between adjacent ones of the insulating patterns and between the adjacent ones of the bit line structures;

forming a preliminary contact pattern in the contact hole, the preliminary contact pattern exposing an upper sidewall of the hard mask pattern;

after forming the preliminary contact pattern, forming a second sacrificial spacer connected to a portion of the first sacrificial spacer in the contact hole, the second sacrificial spacer covering the upper sidewall of the hard mask pattern and upper sidewalls of the insulating patterns,

recessing a top surface of the preliminary contact pattern to form a contact pattern, the contact pattern having a top surface positioned lower than a top surface of the conductive pattern;

forming a landing pad connected to the contact pattern, forming the landing pad comprising forming a recess region exposing a portion of the second sacrificial spacer; and

removing the first and second sacrificial spacers to form first and second air gaps.

2. The method of claim 1 , wherein

the first air gap is between the first spacer and the second spacer and extends in the second direction,

the second air gap extends from the first air gap to between the insulating patterns and the landing pad along the first direction.

3. The method of claim 1 , wherein a thickness of the first sacrificial spacer is greater than a thickness of the second sacrificial spacer.

4. The method of claim 1 , wherein top surfaces of the insulating patterns are located at substantially the same level as top surfaces of the hard mask patterns of the bit line structures.

5. The method of claim 1 , wherein the contact hole exposes a portion of the semiconductor substrate.

6. The method of claim 1 , wherein after forming the preliminary contact pattern, the first sacrificial spacer has first portions adjacent to the preliminary contact pattern and second portions adjacent to the insulating patterns, and

wherein a height of the first sacrificial spacer is greater at the second portions than at the first portions.

7. The method of claim 6 , wherein the second sacrificial spacer is in contact with the first portions of the first sacrificial spacer.

8. The method of claim 6 , wherein the second sacrificial spacer has a ring shape surrounding the contact pattern in a plan view.

9. The method of claim 1 , wherein forming the landing pad comprises:

forming a conductive layer filling the contact hole;

forming a mask pattern on the conductive layer; and

etching the conductive layer using the mask pattern as an etch mask.

10. The method of claim 1 , wherein an upper portion of the landing pad partially overlaps with a portion of a respective one of the bit line structures, and

wherein an upper width of the landing pad is greater than a distance between adjacent ones of the bit line structures.

11. A method of manufacturing a semiconductor device, comprising:

forming word lines extending in a first direction in a semiconductor substrate;

forming bit line structures extending in a second direction intersecting the first direction;

forming spacer structures extending along sidewalls of each of the bit line structures, each of the spacer structures comprising first and second spacers and a first sacrificial spacer between the first and second spacers;

forming a second sacrificial spacer having a ring shape in a plan view, the second sacrificial spacer contacting a portion of the first sacrificial spacer between adjacent ones of the bit line structures;

forming landing pads on the bit line structures defining a recess region exposing a portion of the second sacrificial spacer; and

removing the first and second sacrificial spacers to form first and second air gaps.

12. The method of claim 11 , wherein the second air gap surrounds one of the landing pads in a plan view.

13. The method of claim 11 , wherein the first air gap continuously extends along the sidewalls of the bit line structures.

14. The method of claim 11 , further comprising, before forming the second sacrificial spacer, forming insulating patterns spaced apart from each other between adjacent ones of the bit line structures,

wherein the second sacrificial spacer covers upper sidewalls of the adjacent ones of the bit line structures and upper sidewalls of adjacent ones of the insulating patterns.

15. The method of claim 14 , further comprising, before forming the second sacrificial spacer, forming a preliminary contact pattern connected to a portion of the semiconductor substrate, the preliminary contact pattern disposed between the adjacent ones of the insulating patterns and between the adjacent ones of the bit line structures.

16. The method of claim 15 , wherein the first sacrificial spacer has first portions adjacent to the preliminary contact pattern and second portions adjacent to the insulating patterns, after forming the preliminary contact pattern, and

wherein a height of the first sacrificial spacer is greater at the second portions than at the first portions.

17. The method of claim 16 , further comprising recessing a top surface of the preliminary contact pattern to form a contact pattern, after forming the second sacrificial spacer,

wherein the contact pattern has a top surface positioned lower than top surfaces of the first portions of the first sacrificial spacer.

18. A method of manufacturing a semiconductor device, comprising:

forming word lines extending in a first direction in a semiconductor substrate;

forming bit line structures crossing over the word lines and extending in a second direction intersecting the first direction;

sequentially forming a first spacer, a first sacrificial spacer, and a second spacer on opposite sidewalls of each of the bit line structures;

forming insulating patterns arranged along the second direction between the bit line structures to define a contact hole between adjacent ones of the insulating patterns and between the adjacent ones of the bit line structures;

forming a preliminary contact pattern in the contact hole, the preliminary contact pattern exposing an upper sidewall of a hard mask pattern and upper sidewalls of the insulating patterns;

after forming the preliminary contact pattern, forming a second sacrificial spacer connected to a portion of the first sacrificial spacer in the contact hole, the second sacrificial spacer covering the upper sidewall of the hard mask pattern and the upper sidewalls of the insulating patterns,

forming a third spacer on the second sacrificial spacer;

recessing a top surface of the preliminary contact pattern to form a contact pattern in the contact hole;

forming a conductive layer filling the contact hole;

forming mask patterns on the conductive layer

etching the conductive layer using the mask patterns as an etch mask to form a landing pad on the contact pattern, a portion of the second sacrificial spacer exposed by the landing pad; and

after forming the landing pad, removing the first and second sacrificial spacers to form first and second air gaps.

19. The method of claim 18 , wherein

the first air gap is between the first spacer and the second spacer and extends in the second direction,

the second air gap extends from the first air gap to between the first spacer and the third spacer.

20. The method of claim 18 , wherein the second air gap surrounds the landing pad in plan view.