Method of forming self aligned grids in BSI image sensor

1. A method comprising:

depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein;

forming a grid of trenches, wherein a trench passes through the first dielectric layer and extends into the substrate;

filling in the trenches with a dielectric material to create a trench isolation grid;

etching back the dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid; and

filling in the recesses with a metallic material to create a metallic grid that is aligned with the trench isolation grid.

2. The method of claim 1 , further comprising:

removing at least part of the first dielectric layer to expose at least part of an interior region of metallic grid segments in the metallic grid.

3. The method of claim 1 , further comprising:

removing at least part of the first dielectric layer and at least part of the substrate, to expose at least part of an interior region of metallic grid segments in the metallic grid, until a bottom of the metallic grid is vertically separated from a surface of the substrate by a predetermined distance.

4. The method of claim 1 , wherein forming the grid of trenches comprises:

depositing a layer of silicon nitride over the first dielectric layer;

forming a mask pattern in the layer of silicon nitride; and

etching through the first dielectric layer and etching into the substrate according to the mask pattern in the layer of silicon nitride.

5. The method of claim 1 , further comprising:

forming a high absorption structure in a part of the back surface of the substrate, wherein the first dielectric layer is deposited on the high absorption structure in the part of the back surface of the substrate.

6. The method of claim 5 , further comprising:

removing at least part of the first dielectric layer until a surface of the high absorption structure is exposed.

7. The method of claim 1 , wherein the first dielectric layer comprises a layer of oxide.

8. The method of claim 1 , wherein the metallic material comprises tungsten.

9. The method of claim 1 , further comprising:

depositing a layer of high-k dielectric material over the back surface of the substrate, wherein the first dielectric layer is deposited on the layer of high-k dielectric material.

10. The method of claim 1 , further comprising:

lining inner surfaces of the recesses with a barrier layer before filling in the recesses with the metallic material.

11. A method comprising:

depositing a dielectric layer overlying a photodiode in a substrate;

performing a first etch into the dielectric layer and the substrate to form a first trench and a second trench bordering the photodiode respectively on opposite sides of the photodiode, wherein the dielectric layer and the substrate define a common sidewall in the first trench;

forming a trench isolation structure in the first and second trenches and directly contacting the common sidewall; and

forming a conductive grid structure overlying the trench isolation structure in the first and second trenches and directly contacting the common sidewall.

12. The method of claim 11 , wherein the forming of the conductive grid structure comprises:

depositing a conductive barrier layer lining the first and second trenches over the trench isolation structure; and

depositing a metallic layer filling the first and second trenches over the conductive barrier layer.

13. The method of claim 11 , further comprising:

depositing a high-k dielectric layer overlying the photodiode, wherein the dielectric layer is deposited over the high-k dielectric layer, wherein the first etch is also performed into the high-k dielectric layer, and wherein the high-k dielectric layer partially defines the common sidewall.

14. The method of claim 11 , wherein the common sidewall has a planar profile.

15. The method of claim 11 , further comprising:

depositing a hard mask layer overlying the dielectric layer, wherein the first etch is performed with the hard mask layer in place, wherein the hard mask layer partially defines the common sidewall, and wherein the forming of the conductive grid structure comprises a planarization that planarizes a top surface of the conductive grid structure and removes the hard mask layer.

16. A method comprising:

depositing a dielectric layer overlying a photodiode in a substrate;

performing a first etch into the dielectric layer and the substrate to form a grid of trenches surrounding the photodiode;

forming a trench isolation structure partially filling the trenches;

depositing a conductive layer partially filling the trenches over the trench isolation structure, wherein the conductive layer comprises: a conductive barrier layer lining the trenches; and a metallic layer overlying the conductive barrier layer; and

performing a planarization into the conductive layer, including into the conductive barrier layer and the metallic layer, to recess a top surface of the conductive layer so the top surface of the conductive layer is level with a top surface of the dielectric layer.

17. The method of claim 16 , further comprising:

performing a second etch into the dielectric layer to recess the top surface of the dielectric layer relative to the top surface of the conductive layer after the planarization.

18. The method of claim 16 , wherein the forming of the trench isolation structure comprises:

depositing a dielectric material filling the trenches; and

performing a second etch into the dielectric material to recess a top surface of the dielectric material relative to the top surface of the dielectric layer.

19. The method of claim 16 , further comprising:

depositing a high-k dielectric layer overlying the photodiode and having a top and a bottom both with saw-toothed profiles, wherein the dielectric layer is deposited over the high-k dielectric layer, and wherein the first etch is also performed into the high-k dielectric layer to form the trenches extending through the high-k dielectric layer.

20. The method of claim 16 , wherein the conductive layer and the trench isolation structure share a common width in the trenches.