Hybrid complementary field effect transistor device

1. A stacked transistor device, comprising:

a nanosheet transistor device on a substrate; and

a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.

2. The stacked transistor device of claim 1 , wherein the nanosheet transistor device and the fin field effect transistor device include a shared gate structure.

3. The stacked transistor device of claim 2 , further comprising a gate contact on and in electrical contact with the shared gate structure.

4. The stacked transistor device of claim 3 , further comprising wherein the nanosheet transistor device includes two nanosheet source/drain regions on opposite sides of the shared gate structure, and the fin field effect transistor device includes two fin source/drains on opposite sides of the shared gate structure, such that the two nanosheet source/drain regions are on different sides of the shared gate structure than the two fin source/drains.

5. The stacked transistor device of claim 4 , further comprising a nanosheet source/drain contact on and in electrical communication with each of the two nanosheet source/drain regions, and a fin source/drain contact on and in electrical communication with each of the two fin source/drains, wherein the nanosheet source/drain contacts are on different sides of the gate contact and shared gate structure than the two fin source/drain contacts.

6. A stacked transistor device, comprising:

a plurality of stacked semiconductor channel segments on a substrate;

a nanosheet source/drain region on each of opposite sides of the plurality of stacked semiconductor channel segments;

a fin section over the plurality of stacked semiconductor channel segments;

a fin source/drain on each of opposite sides of the fin section;

a shared gate structure on the fin section and the plurality of stacked semiconductor channel segments, wherein the two nanosheet source/drain regions are on opposite sides of the shared gate structure, and the two fin source/drains are on opposite sides of the shared gate structure, such that the two nanosheet source/drain regions are on different sides of the shared gate structure than the two fin source/drains.

7. The stacked transistor device of claim 6 , further comprising a protective fill on a portion of the fin section.

8. The stacked transistor device of claim 7 , further comprising a gate contact on and in electrical contact with the shared gate structure.

9. The stacked transistor device of claim 8 , further comprising a nanosheet source/drain contact on and in electrical communication with each of the nanosheet source/drain regions, and a fin source/drain contact on and in electrical communication with each of the fin source/drains, wherein the nanosheet source/drain contacts are on different sides of the gate contact and shared gate structure than the two fin source/drain contacts.

10. The stacked transistor device of claim 9 , further comprising a bottom dielectric shell on a lower portion of the shared gate structure, wherein a portion of the bottom dielectric shell electrically separates the fin source/drains from lower portion of the shared gate structure.

11. The stacked transistor device of claim 9 , further comprising an insulating layer between the substrate and the shared gate structure.

12. A method of forming a stacked transistor device, comprising:

forming a plurality of stacked semiconductor channel segments and a fin section over the plurality of stacked semiconductor channel segments on a substrate;

forming a nanosheet source/drain region on each of opposite sides of the plurality of stacked semiconductor channel segments;

forming a fin source/drain on each of opposite sides of the fin section;

forming a shared gate structure on the fin section and the plurality of stacked semiconductor channel segments, wherein the two nanosheet source/drain regions are on opposite sides of the shared gate structure, and the two fin source/drains are on opposite sides of the shared gate structure, such that the two nanosheet source/drain regions are on different sides of the shared gate structure than the two fin source/drains.

13. The method of claim 12 , further comprising forming a bottom dielectric shell on a lower portion of the shared gate structure, wherein a portion of the bottom dielectric shell electrically separates the fin source/drains from lower portion of the shared gate structure.

14. The method of claim 13 , further comprising forming a cover layer on the fin source/drains and the bottom dielectric shell.

15. The method of claim 14 , further comprising forming a nanosheet source/drain contact on and in electrical communication with each of the nanosheet source/drain regions.

16. The method of claim 15 , further comprising forming a fin source/drain contact on and in electrical communication with each of the fin source/drains.

17. The method of claim 16 , further comprising forming a gate contact on and in electrical contact with the shared gate structure.

18. The method of claim 17 , wherein the nanosheet source/drain contacts are on different sides of the gate contact and shared gate structure than the two fin source/drain contacts.

19. The method of claim 18 , further comprising forming a dielectric fill layer on the fin source/drains and the nanosheet source/drain regions.

20. The method of claim 19 , further comprising forming a protective fill on a portion of the fin section and the dielectric fill layer.